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From:
Hrvoje Popovski <hrvoje@srce.hr>
Subject:
Re: Adjust amd64 IPLs
To:
Mark Kettenis <mark.kettenis@xs4all.nl>, tech@openbsd.org
Date:
Tue, 2 Jan 2024 11:01:16 +0100

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On 1.1.2024. 20:27, Hrvoje Popovski wrote:
> Hi,
> 
> I'm having 24 core box with 4 ix, 2 mcx and 2 bnxt. Without this diff in
> dmesg i can see


Same box but with 2 ix, 2 mcx, 2 bnxt and 4 ixl. Without diff I can see
only 3 ixl interfaces

ixl0 at pci21 dev 0 function 0 "Intel X710 SFP+" rev 0x01: port 3, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c0

ixl1 at pci21 dev 0 function 1 "Intel X710 SFP+" rev 0x01: port 2, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c1

ixl2 at pci21 dev 0 function 2 "Intel X710 SFP+" rev 0x01: port 0, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c2

ixl3 at pci21 dev 0 function 3 "Intel X710 SFP+" rev 0x01: port 1, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c3
failed to allocate interrupt slot for PIC msix pin -2143223033
ixl3: unable to establish interrupt 7



with this diff I see all four ixl interfaces

ixl0 at pci21 dev 0 function 0 "Intel X710 SFP+" rev 0x01: port 3, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c0
ixl1 at pci21 dev 0 function 1 "Intel X710 SFP+" rev 0x01: port 2, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c1
ixl2 at pci21 dev 0 function 2 "Intel X710 SFP+" rev 0x01: port 0, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c2
ixl3 at pci21 dev 0 function 3 "Intel X710 SFP+" rev 0x01: port 1, FW
8.3.64775 API 1.13, msix, 8 queues, address 3c:fd:fe:b3:26:c3