> Date: Wed, 6 Mar 2024 15:01:30 +0800
> From: Kevin Lo <kevlo@kevlo.org>
> 
> On Mon, Mar 04, 2024 at 04:24:18PM +0100, Mark Kettenis wrote:
> > 
> > > Date: Mon, 4 Mar 2024 21:09:17 +0800
> > > From: Kevin Lo <kevlo@kevlo.org>
> > > 
> > > On Sun, Mar 03, 2024 at 11:28:20AM +0100, Mark Kettenis wrote:
> > > > 
> > > > > Date: Sun, 3 Mar 2024 11:47:35 +0800
> > > > > From: Kevin Lo <kevlo@kevlo.org>
> > > > > 
> > > > > Hi,
> > > > > 
> > > > > dwxe(4) works on my Nezha board, I'd like to enable it.
> > > > > ok?
> > > > 
> > > > We need to implement the clock and reset that it complains about...
> > > 
> > > My bad, I missed adding EMAC clocks.  The diff below adds EMAC clocks for
> > > Allwinner D1 and enable dwxe(4).
> > > 
> > > ok?
> > 
> > Sorry, but you also need to implement getting the clock frequency for
> > this clock.
> 
> Hi Mark,
> 
> First of all, I'm really sorry for wasting your precious time reviewing my
> incorrect patch.  This patch adds support for Allwinner D1's ethernet
> controller clocks and reset.
> 
> ok?

No worries.  Looks good now.  ok kettenis@

While this does change a header file, it isn't one that userland
should be using.  But please wait for an explicit ok from Theo.


> Index: sys/arch/riscv64/conf/GENERIC
> ===================================================================
> RCS file: /cvs/src/sys/arch/riscv64/conf/GENERIC,v
> retrieving revision 1.49
> diff -u -p -u -p -r1.49 GENERIC
> --- sys/arch/riscv64/conf/GENERIC	2 Feb 2024 12:09:18 -0000	1.49
> +++ sys/arch/riscv64/conf/GENERIC	6 Mar 2024 06:04:44 -0000
> @@ -101,6 +101,7 @@ ehci*		at fdt?
>  cad*		at fdt?
>  dwge*		at fdt?
>  dwqe*		at fdt?
> +dwxe*		at fdt?
>  dwiic*		at fdt?
>  iic*		at dwiic?
>  dwmmc*		at fdt?
> Index: sys/arch/riscv64/conf/RAMDISK
> ===================================================================
> RCS file: /cvs/src/sys/arch/riscv64/conf/RAMDISK,v
> retrieving revision 1.42
> diff -u -p -u -p -r1.42 RAMDISK
> --- sys/arch/riscv64/conf/RAMDISK	2 Feb 2024 12:09:18 -0000	1.42
> +++ sys/arch/riscv64/conf/RAMDISK	6 Mar 2024 06:04:44 -0000
> @@ -91,6 +91,7 @@ ehci*		at fdt?
>  cad*		at fdt?
>  dwge*		at fdt?
>  dwqe*		at fdt?
> +dwxe*		at fdt?
>  
>  dwmmc*		at fdt?
>  sdmmc*		at dwmmc?
> Index: sys/dev/fdt/sxiccmu.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
> retrieving revision 1.37
> diff -u -p -u -p -r1.37 sxiccmu.c
> --- sys/dev/fdt/sxiccmu.c	4 Mar 2024 04:11:52 -0000	1.37
> +++ sys/dev/fdt/sxiccmu.c	6 Mar 2024 06:04:44 -0000
> @@ -1265,12 +1265,15 @@ sxiccmu_a80_get_frequency(struct sxiccmu
>  #define D1_RISCV_CLK_SEL_HOSC		(0 << 24)
>  #define D1_RISCV_CLK_SEL_PLL_CPU	(5 << 24)
>  #define D1_RISCV_DIV_CFG_FACTOR_M(x)	(((x) >> 0) & 0x1f)
> +#define D1_PSI_CLK_REG			0x0510
> +#define D1_PSI_CLK_FACTOR_N(x)		(((x) >> 8) & 0x3)
> +#define D1_PSI_CLK_FACTOR_M(x)		(((x) >> 0) & 0x3)
>  
>  uint32_t
>  sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
>  {
>  	uint32_t parent;
> -	uint32_t reg;
> +	uint32_t reg, freq;
>  	uint32_t m, n;
>  
>  	switch (idx) {
> @@ -1301,6 +1304,13 @@ sxiccmu_d1_get_frequency(struct sxiccmu_
>  		}
>  		m = D1_RISCV_DIV_CFG_FACTOR_M(reg) + 1;
>  		return sxiccmu_ccu_get_frequency(sc, &parent) / m;
> +	case D1_CLK_PSI_AHB:
> +		reg = SXIREAD4(sc, D1_PSI_CLK_REG);
> +		/* assume PLL_PERIPH0 source */
> +		freq = sxiccmu_d1_get_frequency(sc, D1_CLK_PLL_PERIPH0);
> +		m = D1_PSI_CLK_FACTOR_M(reg) + 1;
> +		n = 1 << D1_PSI_CLK_FACTOR_N(reg);
> +		return freq / (m * n);
>  	}
>  
>  	printf("%s: 0x%08x\n", __func__, idx);
> Index: sys/dev/fdt/sxiccmu_clocks.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
> retrieving revision 1.37
> diff -u -p -u -p -r1.37 sxiccmu_clocks.h
> --- sys/dev/fdt/sxiccmu_clocks.h	3 Mar 2024 21:42:41 -0000	1.37
> +++ sys/dev/fdt/sxiccmu_clocks.h	6 Mar 2024 06:04:44 -0000
> @@ -364,6 +364,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_m
>  
>  #define D1_CLK_PLL_CPU		0
>  #define D1_CLK_PLL_PERIPH0	5
> +#define D1_CLK_PSI_AHB		23
>  #define D1_CLK_APB1		25
>  #define D1_CLK_MMC0		56
>  #define D1_CLK_MMC1		57
> @@ -377,6 +378,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_m
>  #define D1_CLK_BUS_UART3	65
>  #define D1_CLK_BUS_UART4	66
>  #define D1_CLK_BUS_UART5	67
> +#define D1_CLK_BUS_EMAC		77
>  #define D1_CLK_USB_OHCI0	97
>  #define D1_CLK_USB_OHCI1	98
>  #define D1_CLK_BUS_OHCI0	99
> @@ -400,6 +402,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_g
>  	[D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 },
>  	[D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 },
>  	[D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 },
> +	[D1_CLK_BUS_EMAC] =  { 0x097c, 0, D1_CLK_PSI_AHB },
>  	[D1_CLK_USB_OHCI0] = { 0x0a70, 31 },
>  	[D1_CLK_USB_OHCI1] = { 0x0a74, 31 },
>  	[D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
> @@ -989,6 +992,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_m
>  #define D1_RST_BUS_UART3	21
>  #define D1_RST_BUS_UART4	22
>  #define D1_RST_BUS_UART5	23
> +#define D1_RST_BUS_EMAC		30
>  #define D1_RST_USB_PHY0		40
>  #define D1_RST_USB_PHY1		41
>  #define D1_RST_BUS_OHCI0	42
> @@ -1006,6 +1010,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_r
>  	[D1_RST_BUS_UART3] = { 0x090c, 19 },
>  	[D1_RST_BUS_UART4] = { 0x090c, 20 },
>  	[D1_RST_BUS_UART5] = { 0x090c, 21 },
> +	[D1_RST_BUS_EMAC] =  { 0x097c, 16 },
>  	[D1_RST_USB_PHY0] =  { 0x0a70, 30 },
>  	[D1_RST_USB_PHY1] =  { 0x0a74, 30 },
>  	[D1_RST_BUS_OHCI0] = { 0x0a8c, 16 },
> 
> 
> OpenBSD 7.5 (GENERIC.MP) #1: Wed Mar  6 14:09:05 CST 2024
>     root@nezha.kevlo.org:/usr/src/sys/arch/riscv64/compile/GENERIC.MP
> real mem  = 1073741824 (1024MB)
> avail mem = 1008459776 (961MB)
> SBI: OpenSBI v1.2, SBI Specification Version 1.0
> random: good seed from bootblocks
> mainbus0 at root: Allwinner D1 Nezha
> cpu0 at mainbus0: T-Head arch 0 imp 0 rv64imafdc
> intc0 at cpu0
> cpu0: 32KB 64b/line 128-way L1 I-cache, 32KB 64b/line 256-way L1 D-cache
> "fit-images" at mainbus0 not configured
> "dcxo-clk" at mainbus0 not configured
> simplebus0 at mainbus0: "soc"
> sxipio0 at simplebus0: 88 pins
> sxiccmu0 at simplebus0
> plic0 at simplebus0
> sxitimer0 at simplebus0: 24000 kHz
> sxidog0 at simplebus0
> com0 at simplebus0: dw16550
> com0: console
> com1 at simplebus0: dw16550
> "i2c" at simplebus0 not configured
> "syscon" at simplebus0 not configured
> "dma-controller" at simplebus0 not configured
> "efuse" at simplebus0 not configured
> "crypto" at simplebus0 not configured
> "dram-controller" at simplebus0 not configured
> sximmc0 at simplebus0
> sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
> sximmc1 at simplebus0
> sdmmc1 at sximmc1: 4-bit, sd high-speed, mmc high-speed, dma
> "usb" at simplebus0 not configured
> "phy" at simplebus0 not configured
> ehci0 at simplebus0
> usb0 at ehci0: USB revision 2.0
> uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> ohci0 at simplebus0: version 1.0
> ehci1 at simplebus0
> usb1 at ehci1: USB revision 2.0
> uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
> ohci1 at simplebus0: version 1.0
> dwxe0 at simplebus0: address a2:d6:d9:50:21:75
> rgephy0 at dwxe0 phy 1: RTL8169S/8110S/8211 PHY, rev. 6
> "clock-controller" at simplebus0 not configured
> "mixer" at simplebus0 not configured
> "mixer" at simplebus0 not configured
> "phy" at simplebus0 not configured
> "tcon-top" at simplebus0 not configured
> "lcd-controller" at simplebus0 not configured
> "lcd-controller" at simplebus0 not configured
> "power-controller" at simplebus0 not configured
> "clock-controller" at simplebus0 not configured
> sxirtc0 at simplebus0
> sxidog1 at simplebus0
> sxidog2 at simplebus0
> gpio0 at sxipio0: 32 pins
> gpio1 at sxipio0: 32 pins
> gpio2 at sxipio0: 32 pins
> gpio3 at sxipio0: 32 pins
> gpio4 at sxipio0: 32 pins
> gpio5 at sxipio0: 32 pins
> gpio6 at sxipio0: 32 pins
> usb2 at ohci0: USB revision 1.0
> uhub2 at usb2 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00 addr 1
> usb3 at ohci1: USB revision 1.0
> uhub3 at usb3 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00 addr 1
> "opp-table-cpu" at mainbus0 not configured
> "pmu" at mainbus0 not configured
> "vcc" at mainbus0 not configured
> "vcc-3v3" at mainbus0 not configured
> "usbvbus" at mainbus0 not configured
> "vdd-cpu" at mainbus0 not configured
> "wifi-pwrseq" at mainbus0 not configured
> "binman" at mainbus0 not configured
> sdmmc1: can't enable card
> umass0 at uhub1 port 1 configuration 1 interface 0 "USB SanDisk 3.2Gen1" rev 2.10/1.00 addr 2
> umass0: using SCSI over Bulk-Only
> scsibus0 at umass0: 2 targets, initiator 0
> sd0 at scsibus0 targ 1 lun 0: <USB, SanDisk 3.2Gen1, 1.00> removable serial.078155838107a728426f
> sd0: 58680MB, 512 bytes/sector, 120176640 sectors
> vscsi0 at root
> scsibus1 at vscsi0: 256 targets
> softraid0 at root
> scsibus2 at softraid0: 256 targets
> root on sd0a (f1001a7ea623952a.a) swap on sd0b dump on sd0b
> sxiccmu_d1_set_frequency: 0x00000084
> cpu0: clock not implemented
>