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MANGOPI - can you help me finish this TRNG?
Hi @openbsd.org,
I have written a sxicrypto.c driver since 6AM this morning while managing
to still be there for family. Happy Easter and happy april fools day!
I will attempt to relay you the manpage first, and then the patch against
/sys directory. I have edited some other work out (for the bl-808 that I'm
working on).
Right now it works afaik, but it causes a irq storm of sorts I suspect. I
used ccp(4) and octcrypto(4) as an example as well as other sxi*.c files.
ccp seems to timer_add_ms() at 100, where octcrypto uses 10 I wonder if that
is too much but anyhow, I followed ccp(4) for that.
please CC me until I get around to subscribing to tech@ again.
Best regards,
-pjp
manpage ------->
.\" $OpenBSD$
.\"
.\" Copyright (c) 2024 Peter J. Philipp
.\"
.\" Permission to use, copy, modify, and distribute this software for any
.\" purpose with or without fee is hereby granted, provided that the above
.\" copyright notice and this permission notice appear in all copies.
.\"
.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
.\"
.Dd $Mdocdate: April 1 2024 $
.Dt SXICRYPTO 4
.Os
.Sh NAME
.Nm sxicrypto
.Nd D1 crypto and trng device
.Sh SYNOPSIS
.Cd "sxicrypto* at fdt?"
.Sh DESCRIPTION
The
.Nm
driver provides support for the TRNG device integrated in Allwinner Technology
D1 SoCs. All supported modes on the D1 are turned off except the TRNG.
.Sh HISTORY
The
.Nm
device driver first appeared in
.Ox 7.6 .
<-------------------
and here is the source:
? sys/arch/arm64/compile/GENERIC.MP/Makefile
? sys/arch/riscv64/compile/MANGOPI
? sys/arch/riscv64/compile/RAMANGO
? sys/arch/riscv64/conf/RAMANGO
? sys/arch/riscv64/dev/bflbtimer.c
? sys/arch/riscv64/dev/bflbuart.c
Index: sys/arch/riscv64/conf/MANGOPI
===================================================================
RCS file: sys/arch/riscv64/conf/MANGOPI
diff -N sys/arch/riscv64/conf/MANGOPI
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/arch/riscv64/conf/MANGOPI 1 Apr 2024 19:12:53 -0000
@@ -0,0 +1,305 @@
+# $OpenBSD: GENERIC,v 1.50 2024/03/07 01:05:07 kevlo Exp $
+#
+# For further information on compiling OpenBSD kernels, see the config(8)
+# man page.
+#
+# For further information on hardware support for this architecture, see
+# the intro(4) man page. For further information about kernel options
+# for this architecture, see the options(4) man page. For an explanation
+# of each device driver in this file see the section 4 man page for the
+# device.
+
+machine riscv64
+include "../../../conf/GENERIC"
+maxusers 80
+
+option PCIVERBOSE
+option USER_PCICONF
+
+makeoptions KERNEL_BASE_PHYS="0x00200000"
+makeoptions KERNEL_BASE_VIRT="0xffffffc000200000"
+#option DEBUG
+#option DEBUG_AUTOCONF
+#option DEBUG_INTC
+#option DEBUG_TIMER
+
+option WSDISPLAY_COMPAT_USL
+option WSDISPLAY_COMPAT_RAWKBD
+option WSDISPLAY_DEFAULTSCREENS=6
+
+
+config bsd swap generic
+
+#
+# Definition of system
+#
+
+# mainbus
+mainbus0 at root
+
+# cpu0
+cpu0 at mainbus0
+intc0 at cpu0
+
+# NS16550 compatible serial ports
+com* at fdt?
+
+# Allwinner SoCs
+sxiccmu* at fdt? early 1
+sxidog* at fdt?
+sximmc* at fdt?
+sdmmc* at sximmc?
+sxipio* at fdt? early 1
+gpio* at sxipio?
+sxirtc* at fdt?
+sxitimer* at fdt?
+sxicrypto* at fdt?
+
+# PolarFire SoCs
+cdsdhc* at fdt?
+sdmmc* at cdsdhc?
+mpfclock* at fdt? early 1
+mpfgpio* at fdt?
+gpio* at mpfgpio?
+mpfiic* at fdt?
+iic* at mpfiic?
+
+# SiFive SoCs
+sfclock* at fdt? early 1 # PRCI
+sfcc* at fdt? early 1 # L2 Cache Controller
+sfgpio* at fdt?
+sfuart* at fdt?
+
+# StarFive SoCs
+stfclock* at fdt? early 1
+stfpcie* at fdt?
+pci* at stfpcie?
+stfpciephy* at fdt? early 1
+stfpinctrl* at fdt? early 1
+stfrng* at fdt?
+stftemp* at fdt?
+
+#bflbtimer* at fdt?
+#bflbuart* at fdt?
+
+virtio* at fdt?
+virtio* at pci?
+vio* at virtio? # Network
+vioblk* at virtio?
+vioscsi* at virtio? # Disk (SCSI)
+#viomb* at virtio? # Memory Ballooning
+viornd* at virtio? # Random Source
+
+# simplebus0
+simplebus* at fdt?
+# Platform Level Interrupt Controller
+plic* at fdt? early 1
+
+syscon* at fdt? early 1
+gfrtc* at fdt?
+gpiorestart* at fdt?
+
+ohci* at fdt?
+ehci* at fdt?
+
+cad* at fdt?
+dwge* at fdt?
+dwqe* at fdt?
+dwxe* at fdt?
+dwiic* at fdt?
+iic* at dwiic?
+dwmmc* at fdt?
+sdmmc* at dwmmc?
+
+dwpcie* at fdt?
+pci* at dwpcie?
+pciecam* at fdt?
+pci* at pciecam?
+
+ociic* at fdt?
+iic* at ociic?
+dapmic* at iic?
+titmp* at iic?
+
+xhci* at fdt?
+
+# PCI
+ppb* at pci? # PCI-PCI bridges
+pci* at ppb?
+
+# DRM devices
+#radeondrm* at pci?
+#drm* at radeondrm?
+#wsdisplay* at radeondrm?
+
+# PCI Ethernet
+em* at pci? # Intel Pro/1000 Ethernet
+bge* at pci? # Broadcom BCM57xx (aka Tigon3)
+oce* at pci? # Emulex OneConnect 10Gb ethernet
+aq* at pci? # Aquantia aQtion Ethernet
+ix* at pci? # Intel 82598EB 10Gb ethernet
+ixl* at pci? # Intel Ethernet 700 Series
+igc* at pci? # Intel I225 Ethernet
+
+# Wireless network cards
+iwm* at pci? # Intel WiFi Link 7xxx
+
+nvme* at pci? # NVMe controllers
+ahci* at pci? # AHCI SATA controllers
+
+scsibus* at scsi?
+sd* at scsibus?
+cd* at scsibus?
+ch* at scsibus?
+uk* at scsibus?
+
+# USB Controllers
+xhci* at pci?
+
+# USB bus support
+usb* at ohci?
+usb* at ehci?
+usb* at xhci?
+
+# USB devices
+uhub* at usb? # USB Hubs
+uhub* at uhub? # USB Hubs
+urng* at uhub? # USB Random Number Generator
+uonerng* at uhub? # Moonbase Otago OneRNG
+umodem* at uhub? # USB Modems/Serial
+ucom* at umodem?
+uvisor* at uhub? # Handspring Visor
+ucom* at uvisor?
+uvscom* at uhub? # SUNTAC Slipper U VS-10U serial
+ucom* at uvscom?
+ubsa* at uhub? # Belkin serial adapter
+ucom* at ubsa?
+uftdi* at uhub? # FTDI FT8U100AX serial adapter
+ucom* at uftdi?
+uplcom* at uhub? # I/O DATA USB-RSAQ2 serial adapter
+ucom* at uplcom?
+umct* at uhub? # MCT USB-RS232 serial adapter
+ucom* at umct?
+uslcom* at uhub? # Silicon Laboratories CP210x serial
+ucom* at uslcom?
+uscom* at uhub? # Simple USB serial adapters
+ucom* at uscom?
+ucrcom* at uhub? # Chromebook serial
+ucom* at ucrcom?
+uark* at uhub? # Arkmicro ARK3116 serial
+ucom* at uark?
+moscom* at uhub? # MosChip MCS7703 serial
+ucom* at moscom?
+umcs* at uhub? # MosChip MCS78x0 serial
+ucom* at umcs?
+uipaq* at uhub? # iPAQ serial adapter
+ucom* at uipaq?
+umsm* at uhub? # Qualcomm MSM EVDO
+ucom* at umsm?
+uchcom* at uhub? # WinChipHead CH341/340 serial
+ucom* at uchcom?
+uticom* at uhub? # TI serial
+ucom* at uticom?
+uxrcom* at uhub? # Exar XR21V1410 serial
+ucom* at uxrcom?
+uaudio* at uhub? # USB Audio
+audio* at uaudio?
+umidi* at uhub? # USB MIDI
+midi* at umidi?
+ulpt* at uhub? # USB Printers
+umass* at uhub? # USB Mass Storage devices
+uhidev* at uhub? # Human Interface Devices
+ums* at uhidev? # USB mouse
+wsmouse* at ums? mux 0
+umt* at uhidev? # USB multitouch touchpad
+wsmouse* at umt? mux 0
+uts* at uhub? # USB touchscreen
+wsmouse* at uts? mux 0
+uwacom* at uhidev? # USB Wacom tablet
+wsmouse* at uwacom? mux 0
+ukbd* at uhidev? # USB keyboard
+wskbd* at ukbd? mux 1
+ucycom* at uhidev? # Cypress serial
+ucom* at ucycom?
+uslhcom* at uhidev? # Silicon Labs CP2110 USB HID UART
+ucom* at uslhcom?
+uhid* at uhidev? # USB generic HID support
+fido* at uhidev? # FIDO/U2F security key support
+ucc* at uhidev? # Consumer Control keyboards
+wskbd* at ucc? mux 1
+ujoy* at uhidev? # USB joystick/gamecontroller support
+uhidpp* at uhidev? # Logitech HID++ Devices
+upd* at uhidev? # USB Power Devices sensors
+aue* at uhub? # ADMtek AN986 Pegasus Ethernet
+atu* at uhub? # Atmel AT76c50x based 802.11b
+axe* at uhub? # ASIX Electronics AX88172 USB Ethernet
+axen* at uhub? # ASIX Electronics AX88179 USB Ethernet
+cue* at uhub? # CATC USB-EL1201A based Ethernet
+kue* at uhub? # Kawasaki KL5KUSB101B based Ethernet
+smsc* at uhub? # SMSC LAN95xx Ethernet
+cdce* at uhub? # CDC Ethernet
+urndis* at uhub? # Remote NDIS Ethernet
+upl* at uhub? # Prolific PL2301/PL2302 host-to-host `network'
+ugl* at uhub? # Genesys Logic GL620USB-A host-to-host `network'
+udav* at uhub? # Davicom DM9601 based Ethernet
+mos* at uhub? # MOSCHIP MCS7730/7830 10/100 Ethernet
+mue* at uhub? # Microchip LAN75xx/LAN78xx Ethernet
+url* at uhub? # Realtek RTL8150L based adapters
+ure* at uhub? # Realtek RTL8152 based adapters
+wi* at uhub? # WaveLAN IEEE 802.11DS
+udsbr* at uhub? # D-Link DSB-R100 radio
+radio* at udsbr? # USB radio
+uberry* at uhub? # Research In Motion BlackBerry
+ugen* at uhub? # USB Generic driver
+uath* at uhub? # Atheros AR5005UG/AR5005UX
+ural* at uhub? # Ralink RT2500USB
+rum* at uhub? # Ralink RT2501USB/RT2601USB
+run* at uhub? # Ralink RT2700U/RT2800U/RT3000U
+mtw* at uhub? # MediaTek MT7601U
+otus* at uhub? # Atheros AR9001U
+athn* at uhub? # Atheros AR9002U
+zyd* at uhub? # Zydas ZD1211
+upgt* at uhub? # Conexant/Intersil PrismGT SoftMAC USB
+urtw* at uhub? # Realtek 8187
+rsu* at uhub? # Realtek RTL8188SU/RTL8191SU/RTL8192SU
+urtwn* at uhub? # Realtek RTL8188CU/RTL8192CU
+udcf* at uhub? # Gude Expert mouseCLOCK
+umb* at uhub? # Mobile Broadband Interface Model
+uthum* at uhidev? # TEMPerHUM sensor
+ugold* at uhidev? # gold TEMPer sensor
+utrh* at uhidev? # USBRH sensor
+utwitch* at uhidev? # YUREX BBU sensor
+uoakrh* at uhidev? # Toradex OAK temp and rel humidity
+uoaklux* at uhidev? # Toradex OAK LUX
+uoakv* at uhidev? # Toradex OAK 10V sensor
+uvideo* at uhub? # USB Video
+video* at uvideo?
+utvfu* at uhub? # Fushicai Audio-Video Grabber
+video* at utvfu?
+audio* at utvfu?
+udl* at uhub? # DisplayLink USB displays
+wsdisplay* at udl?
+bwfm* at uhub? # Broadcom FullMAC
+
+acphy* at mii? # Altima AC101 PHYs
+amphy* at mii? # AMD 79C873 PHYs
+atphy* at mii? # Attansic F1 PHYs
+bmtphy* at mii? # Broadcom 10/100 PHYs
+brgphy* at mii? # Broadcom Gigabit PHYs
+eephy* at mii? # Marvell 88E1000 series PHY
+rgephy* at mii? # Realtek 8169S/8110S PHY
+rlphy* at mii? # Realtek 8139 internal PHYs
+sqphy* at mii? # Seeq 8x220 PHYs
+ukphy* at mii? # "unknown" PHYs
+urlphy* at mii? # Realtek RTL8150L internal PHY
+ytphy* at mii? # MotorComm YT8511 PHY
+
+# I2C devices
+axppmic* at iic? # AXP15060 PMIC
+
+# Pseudo-Devices
+pseudo-device openprom
+pseudo-device hotplug 1 # devices hot plugging
+
+# mouse & keyboard multiplexor pseudo-devices
+pseudo-device wsmux 2
Index: sys/arch/riscv64/conf/RAMDISK
===================================================================
RCS file: /cvs/src/sys/arch/riscv64/conf/RAMDISK,v
retrieving revision 1.43
diff -u -p -u -r1.43 RAMDISK
--- sys/arch/riscv64/conf/RAMDISK 7 Mar 2024 01:05:07 -0000 1.43
+++ sys/arch/riscv64/conf/RAMDISK 1 Apr 2024 19:12:53 -0000
@@ -60,6 +60,7 @@ sfclock* at fdt? early 1 # PRCI
sfcc* at fdt? early 1 # L2 Cache Controller
sfuart* at fdt?
+
# StarFive SoCs
stfclock* at fdt? early 1
stfpcie* at fdt?
@@ -106,6 +107,12 @@ iic* at ociic?
dapmic* at iic?
xhci* at fdt?
+
+
+# Bouffalo Labs BL-808 (Pine64 Ox64)
+#bflbtimer* at fdt?
+#bflbuart* at fdt?
+
# PCI
ppb* at pci? # PCI-PCI bridges
Index: sys/dev/fdt/files.fdt
===================================================================
RCS file: /cvs/src/sys/dev/fdt/files.fdt,v
retrieving revision 1.202
diff -u -p -u -r1.202 files.fdt
--- sys/dev/fdt/files.fdt 27 Mar 2024 15:15:00 -0000 1.202
+++ sys/dev/fdt/files.fdt 1 Apr 2024 19:12:53 -0000
@@ -71,6 +71,10 @@ device sxisid
attach sxisid at fdt
file dev/fdt/sxisid.c sxisid
+device sxicrypto
+attach sxicrypto at fdt
+file dev/fdt/sxicrypto.c sxicrypto
+
device sxisyscon: fdt
attach sxisyscon at fdt
file dev/fdt/sxisyscon.c sxisyscon
Index: sys/dev/fdt/sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.38
diff -u -p -u -r1.38 sxiccmu.c
--- sys/dev/fdt/sxiccmu.c 7 Mar 2024 01:04:16 -0000 1.38
+++ sys/dev/fdt/sxiccmu.c 1 Apr 2024 19:12:53 -0000
@@ -1311,6 +1311,9 @@ sxiccmu_d1_get_frequency(struct sxiccmu_
m = D1_PSI_CLK_FACTOR_M(reg) + 1;
n = 1 << D1_PSI_CLK_FACTOR_N(reg);
return freq / (m * n);
+ case D1_CLK_CE:
+ return 24000000;
+ break;
}
printf("%s: 0x%08x\n", __func__, idx);
Index: sys/dev/fdt/sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.38
diff -u -p -u -r1.38 sxiccmu_clocks.h
--- sys/dev/fdt/sxiccmu_clocks.h 7 Mar 2024 01:04:16 -0000 1.38
+++ sys/dev/fdt/sxiccmu_clocks.h 1 Apr 2024 19:12:53 -0000
@@ -366,6 +366,8 @@ const struct sxiccmu_ccu_bit sun9i_a80_m
#define D1_CLK_PLL_PERIPH0 5
#define D1_CLK_PSI_AHB 23
#define D1_CLK_APB1 25
+#define D1_CLK_CE 33
+#define D1_CLK_BUS_CE 34
#define D1_CLK_MMC0 56
#define D1_CLK_MMC1 57
#define D1_CLK_MMC2 58
@@ -390,6 +392,8 @@ const struct sxiccmu_ccu_bit sun9i_a80_m
#define D1_CLK_HOSC 255
const struct sxiccmu_ccu_bit sun20i_d1_gates[] = {
+ [D1_CLK_CE] = { 0x0680, 31 },
+ [D1_CLK_BUS_CE] = { 0x068c, 0 },
[D1_CLK_MMC0] = { 0x0830, 31 },
[D1_CLK_MMC1] = { 0x0834, 31 },
[D1_CLK_MMC2] = { 0x0838, 31 },
@@ -983,6 +987,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_m
/* D1 */
+#define D1_RST_BUS_CE 4
#define D1_RST_BUS_MMC0 15
#define D1_RST_BUS_MMC1 16
#define D1_RST_BUS_MMC2 17
@@ -1001,6 +1006,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_m
#define D1_RST_BUS_EHCI1 45
const struct sxiccmu_ccu_bit sun20i_d1_resets[] = {
+ [D1_RST_BUS_CE] = { 0x068c, 16 },
[D1_RST_BUS_MMC0] = { 0x084c, 16 },
[D1_RST_BUS_MMC1] = { 0x084c, 17 },
[D1_RST_BUS_MMC2] = { 0x084c, 18 },
Index: sys/dev/fdt/sxicrypto.c
===================================================================
RCS file: sys/dev/fdt/sxicrypto.c
diff -N sys/dev/fdt/sxicrypto.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/dev/fdt/sxicrypto.c 1 Apr 2024 19:12:53 -0000
@@ -0,0 +1,292 @@
+/* $OpenBSD$ */
+/*
+ * Copyright (c) 2024 Peter J. Philipp <pjp@delphinusdns.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/timeout.h>
+
+#include <machine/fdt.h>
+#include <machine/bus.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_misc.h>
+#include <dev/ofw/fdt.h>
+
+/*
+ * This driver is based on chapter 10 (page 1344) of
+ * https://mainrechner.de/d1-h_user_manual_v1.0.pdf
+ * originally found at https://mangopi.org
+ */
+
+/* Registers */
+#define CE_TDA 0x0 /* task descriptor address */
+#define CE_ICR 0x8 /* interrupt control */
+#define CE_ICR_CHANNEL_0 (1 << 0)
+#define CE_ICR_CHANNEL_1 (1 << 1)
+#define CE_ICR_CHANNEL_2 (1 << 2)
+#define CE_ICR_CHANNEL_3 (1 << 3)
+#define CE_ISR 0x0c /* ISR */
+#define CE_ISR_CHANNEL_0 (1 << 0)
+#define CE_ISR_CHANNEL_1 (1 << 1)
+#define CE_ISR_CHANNEL_2 (1 << 2)
+#define CE_ISR_CHANNEL_3 (1 << 3)
+#define CE_TLR 0x10 /* load register */
+#define CE_TLR_FULL 0x1
+#define CE_TSR 0x14 /* TSR */
+#define CE_TSR_CHANNEL_0 (1 << 0)
+#define CE_TSR_CHANNEL_1 (1 << 1)
+#define CE_TSR_CHANNEL_2 (1 << 2)
+#define CE_TSR_CHANNEL_3 (1 << 3)
+#define CE_CSA 0x24 /* dma current src address */
+#define CE_CDA 0x28 /* dma current dest address */
+#define CE_THRU 0x2c /* throughput status */
+#define CE_THRU_CLR 0x0 /* throughput clear */
+
+#define HREAD4(sc, reg) \
+ (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
+#define HWRITE4(sc, reg, val) \
+ bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+
+struct sxicrypto_softc {
+ struct device sc_dev;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+
+ struct timeout sc_to;
+
+ vaddr_t sc_buf;
+ vaddr_t sc_in_base;
+ paddr_t sc_in_base_p;
+ vaddr_t sc_out_base;
+ paddr_t sc_out_base_p;
+ vaddr_t sc_scratch;
+ paddr_t sc_scratch_p;
+};
+
+
+#define SXICRYPTO_TC_INPUT (0 * PAGE_SIZE)
+#define SXICRYPTO_TC_OUTPUT (1 * PAGE_SIZE)
+#define SXICRYPTO_TC_IV (2 * PAGE_SIZE)
+#define SXICRYPTO_TC_TRNG (3 * PAGE_SIZE)
+
+struct sxicrypto_tchain {
+ uint32_t id; /* usually zero */
+ uint32_t common_ctrl;
+
+#define CE_INT_ENA (1 << 31)
+#define CE_ALG_SHIFT 0
+#define CE_ALG_MASK 0x3f
+#define CE_ALG_AES 0x0 /* XXX not implemented */
+#define CE_ALG_MD5 0x10 /* XXX not implemented */
+#define CE_ALG_SHA1 0x11 /* XXX not implemented */
+#define CE_ALG_SHA256 0x13 /* XXX not implemented */
+#define CE_ALG_SHA512 0x15 /* XXX not implemented */
+#define CE_ALG_HMAC_SHA1 0x16 /* XXX not implemented */
+#define CE_ALG_HMAC_SHA256 0x17 /* XXX not implemented */
+#define CE_ALG_TRNG 0x30
+#define CE_ALG_PRNG 0x31 /* XXX not implemented */
+
+ uint32_t sym_ctrl;
+ uint32_t assym_ctrl;
+ uint32_t key_desc;
+ uint32_t iv_desc;
+ uint32_t ctr_desc;
+ uint32_t datalen;
+#define SXICRYPTO_DATALEN (16 * sizeof(uint32_t))
+ uint32_t src_addr0;
+ uint32_t src_len0;
+ uint32_t src_addr1;
+ uint32_t src_len1;
+ uint32_t src_addr2;
+ uint32_t src_len2;
+ uint32_t src_addr3;
+ uint32_t src_len3;
+ uint32_t src_addr4;
+ uint32_t src_len4;
+ uint32_t src_addr5;
+ uint32_t src_len5;
+ uint32_t src_addr6;
+ uint32_t src_len6;
+ uint32_t src_addr7;
+ uint32_t src_len7;
+ uint32_t dst_addr0;
+ uint32_t dst_len0;
+ uint32_t dst_addr1;
+ uint32_t dst_len1;
+ uint32_t dst_addr2;
+ uint32_t dst_len2;
+ uint32_t dst_addr3;
+ uint32_t dst_len3;
+ uint32_t dst_addr4;
+ uint32_t dst_len4;
+ uint32_t dst_addr5;
+ uint32_t dst_len5;
+ uint32_t dst_addr6;
+ uint32_t dst_len6;
+ uint32_t dst_addr7;
+ uint32_t dst_len7;
+ uint32_t next;
+ uint32_t rsvd[3];
+};
+
+int sxicrypto_match(struct device *, void *, void *);
+void sxicrypto_attach(struct device *, struct device *, void *);
+void sxicrypto_rnd(void *arg);
+
+
+const struct cfattach sxicrypto_ca = {
+ sizeof(struct sxicrypto_softc), sxicrypto_match, sxicrypto_attach
+};
+
+struct cfdriver sxicrypto_cd = {
+ NULL, "sxicrypto", DV_DULL
+};
+
+
+int
+sxicrypto_match(struct device *parent, void *match, void *aux)
+{
+ struct fdt_attach_args *faa = aux;
+
+ return (OF_is_compatible(faa->fa_node, "allwinner,sun20i-d1-crypto"));
+}
+
+void
+sxicrypto_attach(struct device *parent, struct device *self, void *aux)
+{
+ struct sxicrypto_softc *sc = (struct sxicrypto_softc *)self;
+ struct fdt_attach_args *faa = aux;
+ struct uvm_constraint_range sxicrypto_constraint = { 0x0, 0xffffffff };
+
+ struct kmem_pa_mode kp;
+
+ if (faa->fa_nreg < 1) {
+ printf(": no registers\n");
+ return;
+ }
+
+ sc->sc_iot = faa->fa_iot;
+ if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
+ faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
+ printf(": can't map registers\n");
+ return;
+ }
+
+ /*
+ * Space for the registers, they work with physical addresses and
+ * only with 32 bit size so we need to put a constraint in there in
+ * case these computers ever have above 4 GB RAM.
+ */
+
+ memset((void*)&kp, 0, sizeof(kp));
+ kp.kp_constraint = &sxicrypto_constraint;
+ kp.kp_zero = 1;
+
+ sc->sc_buf = (vaddr_t)km_alloc((4 * PAGE_SIZE),&kv_any,&kp,&kd_waitok);
+ if (sc->sc_buf == 0x0)
+ panic("%s: km_alloc failed\n", __func__);
+
+ sc->sc_in_base = sc->sc_buf;
+ sc->sc_out_base = (sc->sc_buf + SXICRYPTO_TC_OUTPUT);
+ sc->sc_scratch = (sc->sc_buf + SXICRYPTO_TC_IV);
+
+ pmap_extract(pmap_kernel(), sc->sc_buf, &sc->sc_in_base_p);
+ sc->sc_out_base_p = (sc->sc_in_base_p + SXICRYPTO_TC_OUTPUT);
+ sc->sc_scratch_p = (sc->sc_in_base_p + SXICRYPTO_TC_IV);
+
+ HWRITE4(sc, CE_CSA, sc->sc_in_base_p);
+ HWRITE4(sc, CE_CDA, sc->sc_out_base_p);
+
+ timeout_set(&sc->sc_to, sxicrypto_rnd, sc);
+ timeout_add_sec(&sc->sc_to, 5);
+
+ printf(": TRNG\n");
+}
+
+void
+sxicrypto_rnd(void *arg)
+{
+ struct sxicrypto_softc *sc = arg;
+ struct sxicrypto_tchain *tc = (struct sxicrypto_tchain *)sc->sc_buf;
+#if 1 /* change to debug after */
+ char blank[32];
+ static int tries = 0;
+#endif
+ uint32_t rval, safety;
+ uint64_t value;
+
+ memset((void *)sc->sc_buf, 0, (4 * PAGE_SIZE));
+ tc->common_ctrl = (CE_INT_ENA | CE_ALG_TRNG);
+ tc->iv_desc = (sc->sc_buf + SXICRYPTO_TC_IV);
+ tc->ctr_desc = (sc->sc_buf + SXICRYPTO_TC_OUTPUT);
+ tc->datalen = SXICRYPTO_DATALEN;
+ tc->src_addr0 = 0;
+ tc->src_len0 = 0;
+ tc->dst_addr0 = (sc->sc_buf + SXICRYPTO_TC_TRNG);
+ tc->dst_addr0 = 32; /* 256 bits */
+
+ HWRITE4(sc, CE_TDA, (sc->sc_buf + SXICRYPTO_TC_INPUT));
+ HWRITE4(sc, CE_CSA, sc->sc_in_base_p);
+ HWRITE4(sc, CE_CDA, sc->sc_out_base_p);
+ HWRITE4(sc, CE_ICR, (CE_INT_ENA | CE_ALG_TRNG));
+
+ safety = 0;
+ do {
+ if (safety++ > 1000)
+ break;
+ rval = HREAD4(sc, CE_TLR);
+ delay(10);
+ } while ((rval & CE_TLR_FULL));
+
+ HWRITE4(sc, CE_TLR, (rval | CE_TLR_FULL));
+
+#if 0
+ /* XXX this doesn't seem to work right */
+ safety = 0;
+ do {
+ if (safety++ > 10000)
+ goto out;
+
+ rval = HREAD4(sc, CE_ISR);
+ delay(10);
+ } while ((rval & CE_ISR_CHANNEL_0));
+#endif
+
+ memcpy((void*)&value, (void*)(sc->sc_out_base + 0), sizeof(value));
+ enqueue_randomness(value);
+ memcpy((void*)&value, (void*)(sc->sc_out_base + 8), sizeof(value));
+ enqueue_randomness(value);
+ memcpy((void*)&value, (void*)(sc->sc_out_base + 16), sizeof(value));
+ enqueue_randomness(value);
+ memcpy((void*)&value, (void*)(sc->sc_out_base + 24), sizeof(value));
+ enqueue_randomness(value);
+
+#if 1 /* change to DEBUG after */
+ if ((memcmp((void*)&sc->sc_out_base, blank, sizeof(blank)) == 0) &&
+ (tries++ < 10))
+ printf("%s: entropy is blank!\n", __func__);
+#endif
+
+ timeout_add_msec(&sc->sc_to, 100);
+
+ return;
+//out:
+ printf("%s: timeout\n", __func__);
+}
MANGOPI - can you help me finish this TRNG?