On Thu, Apr 18, 2024 at 04:53:45PM +0200, Mark Kettenis wrote:
> > Date: Thu, 18 Apr 2024 14:21:50 +0200
> > From: Hans-Jörg Höxer <Hans-Joerg_Hoexer@genua.de>
> > 
> > Hi,
> > 
> > I've reworked the support of the AMD Platform Security Processor (PSP)
> > as part of the ccp(4) driver.  It's based on the large diff I sent a
> > month or so ago.
> > 
> > The driver provides a set of ioctls that will be needed for eg. vmd(8)
> > to associated SEV memory encryption with a certain guest and to encrypt
> > pages for that guest on startup (ie. bsd elf image and initial page
> > tables, GDT, stack, etc.).
> > 
> > Things to consider:
> > 
> > - at least the PSP is somewhat machine depend and specific to amd64
> >   AMD cpus; nonetheless the ccp(4) driver is also configure for arm64
> >   GENERIC; so I guess at least the CCP part is also found on arm64 cpus or
> >   devices; so I'm not sure if putting the PSP stuff into ccp(4) make
> >   sense; however both PSP and CCP share the same set of PCI registers
> 
> Yes.  The Opteron A1100 has ccp(4).  A bunch of developers have
> machines with that SoC.  Not sure what functionality besides the RNG
> is implemented on those SoCs.  Maybe the PSP bits should be made
> amd64-specific.

A brief summary of the CCP and the System Control Processor (SCP):
https://old.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-11-day1-epub/HC26.11-4-ARM-Servers-epub/HC26.11.410-Opteron-Seattle-White-AMD-HotChipsAMDSeattle_FINAL.pdf

The RTC is via the SCP, which we interface with through EFI runtime
services.