Hi,

When we forward LRO packets from ix(4) via ixl(4) with an MSS that is
out of range (64 - 9668) the ixl(4) inteface get stucked. This could
happen when two packet with 30 bytes payload each will coalesced by the
ix(4) interface.

The x710 specification said:

	The MSS should not be set to a lower value than 64 or larger
	than 9668 bytes.

Thus, we have to round up/off the MSS to keep it in the specified range.

ok?

bye,
Jan

Index: dev/pci/if_ixl.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_ixl.c,v
diff -u -p -r1.99 if_ixl.c
--- dev/pci/if_ixl.c	7 May 2024 18:35:23 -0000	1.99
+++ dev/pci/if_ixl.c	8 May 2024 08:53:31 -0000
@@ -2854,7 +2854,11 @@ ixl_tx_setup_offload(struct mbuf *m0, st
 
 			hlen += ext.tcphlen;
 
-			outlen = m0->m_pkthdr.ph_mss;
+			/*
+			 * The MSS should not be set to a lower value than 64
+			 * or larger than 9668 bytes.
+			 */
+			outlen = MIN(9668, MAX(64, m0->m_pkthdr.ph_mss));
 			paylen = m0->m_pkthdr.len - ETHER_HDR_LEN - hlen;
 
 			ring = IXL_DMA_KVA(&txr->txr_mem);