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dwqe(4) VLAN offload
On Tue, Jun 4, 2024 at 3:49 PM Stefan Sperling <stsp@stsp.name> wrote:
>
> On Sun, Jun 02, 2024 at 09:55:43PM +1000, Jonathan Matthew wrote:
> > I've only tested the receive side of this so far, on an RK3568 system
> > that doesn't implement the transmit side. A couple of comments below.
>
> > > +#if NVLAN > 0
> > > + /* VLAN tags require an extra Tx context descriptor. */
> > > + if (dwqe_have_tx_vlan_offload(sc) &&
> > > + (m->m_flags & M_VLANTAG) &&
> > > + used + DWQE_NTXSEGS + 2 > left) {
> > > + ifq_set_oactive(ifq);
> > > + break;
> > > + }
> > > +#endif
> >
> > Usually we just check that there's space to fit any possible packet at
> > the top of the loop, rather than dequeueing and checking if that
> > specific packet fits. I think it'd be better to change the check above
> > this one to be 'used + DWQE_NTXSEGS + 2 > left', moving the comment about
> > when an extra descriptor is needed there too.
>
> I didn't want to change the non-VLAN path, but agreed, reserving one
> additional slot won't hurt anyone and keeps things simpler.
>
> > > +#if NVLAN > 0
> > > + /* Enable outer VLAN tag stripping on Rx. */
> > > + reg = dwqe_read(sc, GMAC_VLAN_TAG_CTRL);
> > > + reg |= GMAC_VLAN_TAG_CTRL_EVLRXS | GMAC_VLAN_TAG_CTRL_STRIP_ALWAYS;
> > > + dwqe_write(sc, GMAC_VLAN_TAG_CTRL, reg);
> > > +#endif
> >
> > Would it make sense to do this in dwqe_attach() where the transmit side
> > is configured?
>
> I had put this into a similar place where this setting is applied
> in the Linux driver. However, it still works with your suggestion
> and looks nicer, thanks!
>
> New diff below:
>
>
> diff refs/heads/master refs/heads/dwqe-vlan
> commit - 92119d768f45cf44645fc7f9c2fe90112b6d3f97
> commit + f9140c07b7ab51b0bcca0931d1e4cb573e57e181
> blob - 04cdc69851a5b230b81c8c46244384770207a025
> blob + e7934be3cd39673e470d0affb49a24f1664a4449
> --- sys/dev/ic/dwqe.c
> +++ sys/dev/ic/dwqe.c
> @@ -21,6 +21,7 @@
> */
>
> #include "bpfilter.h"
> +#include "vlan.h"
>
> #include <sys/param.h>
> #include <sys/systm.h>
> @@ -100,6 +101,53 @@ dwqe_have_tx_csum_offload(struct dwqe_softc *sc)
> }
>
> int
> +dwqe_have_tx_vlan_offload(struct dwqe_softc *sc)
> +{
> +#if NVLAN > 0
> + return (sc->sc_hw_feature[0] & GMAC_MAC_HW_FEATURE0_SAVLANINS);
> +#else
> + return 0;
> +#endif
> +}
> +
> +void
> +dwqe_set_vlan_rx_mode(struct dwqe_softc *sc)
> +{
> +#if NVLAN > 0
> + uint32_t reg;
> +
> + /* Enable outer VLAN tag stripping on Rx. */
> + reg = dwqe_read(sc, GMAC_VLAN_TAG_CTRL);
> + reg |= GMAC_VLAN_TAG_CTRL_EVLRXS | GMAC_VLAN_TAG_CTRL_STRIP_ALWAYS;
> + dwqe_write(sc, GMAC_VLAN_TAG_CTRL, reg);
> +#endif
> +}
> +
> +void
> +dwqe_set_vlan_tx_mode(struct dwqe_softc *sc)
> +{
> +#if NVLAN > 0
> + uint32_t reg;
> +
> + reg = dwqe_read(sc, GMAC_VLAN_TAG_INCL);
> +
> + /* Enable insertion of outer VLAN tag. */
> + reg |= GMAC_VLAN_TAG_INCL_INSERT;
> +
> + /*
> + * Generate C-VLAN tags (type 0x8100, 802.1Q). Setting this
> + * bit would result in S-VLAN tags (type 0x88A8, 802.1ad).
> + */
> + reg &= ~GMAC_VLAN_TAG_INCL_CSVL;
> +
> + /* Use VLAN tags provided in Tx context descriptors. */
> + reg |= GMAC_VLAN_TAG_INCL_VLTI;
> +
> + dwqe_write(sc, GMAC_VLAN_TAG_INCL, reg);
> +#endif
> +}
> +
> +int
> dwqe_attach(struct dwqe_softc *sc)
> {
> struct ifnet *ifp;
> @@ -127,6 +175,8 @@ dwqe_attach(struct dwqe_softc *sc)
> bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
>
> ifp->if_capabilities = IFCAP_VLAN_MTU;
> + if (dwqe_have_tx_vlan_offload(sc))
> + ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
> if (dwqe_have_tx_csum_offload(sc)) {
> ifp->if_capabilities |= (IFCAP_CSUM_IPv4 |
> IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 |
> @@ -218,6 +268,14 @@ dwqe_attach(struct dwqe_softc *sc)
> if (!sc->sc_fixed_link)
> dwqe_mii_attach(sc);
>
> + /*
> + * All devices support VLAN tag stripping on Rx but inserting
> + * VLAN tags during Tx is an optional feature.
> + */
> + dwqe_set_vlan_rx_mode(sc);
> + if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
> + dwqe_set_vlan_tx_mode(sc);
> +
> if_attach(ifp);
> ether_ifattach(ifp);
>
> @@ -329,7 +387,8 @@ dwqe_start(struct ifqueue *ifq)
> used = 0;
>
> for (;;) {
> - if (used + DWQE_NTXSEGS + 1 > left) {
> + /* VLAN tags require an extra Tx context descriptor. */
> + if (used + DWQE_NTXSEGS + 2 > left) {
> ifq_set_oactive(ifq);
> break;
> }
> @@ -715,6 +774,21 @@ dwqe_rx_csum(struct dwqe_softc *sc, struct mbuf *m, st
> }
>
> void
> +dwqe_vlan_strip(struct dwqe_softc *sc, struct mbuf *m, struct dwqe_desc *rxd)
> +{
> +#if NVLAN > 0
> + uint16_t tag;
> +
> + if ((rxd->sd_tdes3 & RDES3_RDES0_VALID) &&
> + (rxd->sd_tdes3 & RDES3_LD)) {
> + tag = rxd->sd_tdes0 & RDES0_OVT;
> + m->m_pkthdr.ether_vtag = le16toh(tag);
> + m->m_flags |= M_VLANTAG;
> + }
> +#endif
> +}
> +
> +void
> dwqe_rx_proc(struct dwqe_softc *sc)
> {
> struct ifnet *ifp = &sc->sc_ac.ac_if;
> @@ -763,6 +837,7 @@ dwqe_rx_proc(struct dwqe_softc *sc)
> m->m_pkthdr.len = m->m_len = len;
>
> dwqe_rx_csum(sc, m, rxd);
> + dwqe_vlan_strip(sc, m, rxd);
> ml_enqueue(&ml, m);
> }
>
> @@ -1107,12 +1182,34 @@ dwqe_tx_csum(struct dwqe_softc *sc, struct mbuf *m, st
> txd->sd_tdes3 |= TDES3_CSUM_IPHDR_PAYLOAD_PSEUDOHDR;
> }
>
> +uint16_t
> +dwqe_set_tx_context_desc(struct dwqe_softc *sc, struct mbuf *m, int idx)
> +{
> + uint16_t tag = 0;
> +#if NVLAN > 0
> + struct dwqe_desc *ctxt_txd;
> +
> + if ((m->m_flags & M_VLANTAG) == 0)
> + return 0;
> +
> + tag = m->m_pkthdr.ether_vtag;
> + if (tag) {
> + ctxt_txd = &sc->sc_txdesc[idx];
> + ctxt_txd->sd_tdes3 |= (htole16(tag) & TDES3_VLAN_TAG);
> + ctxt_txd->sd_tdes3 |= TDES3_VLAN_TAG_VALID;
> + ctxt_txd->sd_tdes3 |= (TDES3_CTXT | TDES3_OWN);
> + }
> +#endif
> + return tag;
> +}
> +
> int
> dwqe_encap(struct dwqe_softc *sc, struct mbuf *m, int *idx, int *used)
> {
> struct dwqe_desc *txd, *txd_start;
> bus_dmamap_t map;
> int cur, frag, i;
> + uint16_t vlan_tag = 0;
>
> cur = frag = *idx;
> map = sc->sc_txbuf[cur].tb_map;
> @@ -1128,6 +1225,17 @@ dwqe_encap(struct dwqe_softc *sc, struct mbuf *m, int
> bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
> BUS_DMASYNC_PREWRITE);
>
> + if (dwqe_have_tx_vlan_offload(sc)) {
> + vlan_tag = dwqe_set_tx_context_desc(sc, m, frag);
> + if (vlan_tag) {
> + (*used)++;
> + if (frag == (DWQE_NTXDESC - 1))
> + frag = 0;
> + else
> + frag++;
> + }
> + }
> +
> txd = txd_start = &sc->sc_txdesc[frag];
> for (i = 0; i < map->dm_nsegs; i++) {
> /* TODO: check for 32-bit vs 64-bit support */
> @@ -1140,6 +1248,8 @@ dwqe_encap(struct dwqe_softc *sc, struct mbuf *m, int
> if (i == 0) {
> txd->sd_tdes3 |= TDES3_FS;
> dwqe_tx_csum(sc, m, txd);
> + if (vlan_tag)
> + txd->sd_tdes2 |= TDES2_VLAN_TAG_INSERT;
> }
> if (i == (map->dm_nsegs - 1)) {
> txd->sd_tdes2 |= TDES2_IC;
> blob - ab479d54c139b877b2a111e0f99d267db3a17dc0
> blob + 03f66fca83a72220fb718003aaec576c590448e2
> --- sys/dev/ic/dwqereg.h
> +++ sys/dev/ic/dwqereg.h
> @@ -44,6 +44,19 @@
> #define GMAC_INT_MASK_LPIIM (1 << 10)
> #define GMAC_INT_MASK_PIM (1 << 3)
> #define GMAC_INT_MASK_RIM (1 << 0)
> +#define GMAC_VLAN_TAG_CTRL 0x0050
> +#define GMAC_VLAN_TAG_CTRL_EVLRXS (1 << 24)
> +#define GMAC_VLAN_TAG_CTRL_STRIP_ALWAYS ((1 << 21) | (1 << 22))
> +#define GMAC_VLAN_TAG_DATA 0x0054
> +#define GMAC_VLAN_TAG_INCL 0x0060
> +#define GMAC_VLAN_TAG_INCL_VLTI (1 << 20)
> +#define GMAC_VLAN_TAG_INCL_CSVL (1 << 19)
> +#define GMAC_VLAN_TAG_INCL_DELETE 0x10000
> +#define GMAC_VLAN_TAG_INCL_INSERT 0x20000
> +#define GMAC_VLAN_TAG_INCL_REPLACE 0x30000
> +#define GMAC_VLAN_TAG_INCL_VLT 0x0ffff
> +#define GMAC_VLAN_TAG_INCL_RDWR (1U << 30)
> +#define GMAC_VLAN_TAG_INCL_BUSY (1U << 31)
> #define GMAC_QX_TX_FLOW_CTRL(x) (0x0070 + (x) * 4)
> #define GMAC_QX_TX_FLOW_CTRL_PT_SHIFT 16
> #define GMAC_QX_TX_FLOW_CTRL_TFE (1 << 0)
> @@ -64,6 +77,7 @@
> #define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4)
> #define GMAC_MAC_HW_FEATURE0_TXCOESEL (1 << 14)
> #define GMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16)
> +#define GMAC_MAC_HW_FEATURE0_SAVLANINS (1 << 27)
> #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f)
> #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x1f)
> #define GMAC_MAC_MDIO_ADDR 0x0200
> @@ -230,6 +244,12 @@ struct dwqe_desc {
> uint32_t sd_tdes3;
> };
>
> +/* Tx context descriptor bits (host to device); precedes regular descriptor */
> +#define TDES3_CTXT (1 << 30)
> +#define TDES3_VLAN_TAG_VALID (1 << 16)
> +#define TDES3_VLAN_TAG 0xffff
> +/* Bit 31 is the OWN bit, as in regular Tx descriptor. */
> +
> /* Tx bits (read format; host to device) */
> #define TDES2_HDR_LEN 0x000003ff /* if TSO is enabled */
> #define TDES2_BUF1_LEN 0x00003fff /* if TSO is disabled */
> @@ -250,6 +270,11 @@ struct dwqe_desc {
> #define TDES3_CSUM_IPHDR_PAYLOAD (0x2 << 16)
> #define TDES3_CSUM_IPHDR_PAYLOAD_PSEUDOHDR (0x3 << 16)
> #define TDES3_TSO_EN (1 << 18)
> +#define TDES3_CPC ((1 << 26) | (1 << 27)) /* if TSO is disabled */
> +#define TDES3_CPC_CRC_AND_PAD (0x0 << 26)
> +#define TDES3_CPC_CRC_NO_PAD (0x1 << 26)
> +#define TDES3_CPC_DISABLE (0x2 << 26)
> +#define TDES3_CPC_CRC_REPLACE (0x3 << 26)
> #define TDES3_LS (1 << 28)
> #define TDES3_FS (1 << 29)
> #define TDES3_OWN (1U << 31)
> @@ -268,6 +293,8 @@ struct dwqe_desc {
> #define RDES3_OWN (1U << 31)
>
> /* Rx bits (writeback format; device to host) */
> +#define RDES0_IVT 0xffff0000
> +#define RDES0_OVT 0x0000ffff
> #define RDES1_IP_PAYLOAD_TYPE 0x7
> #define RDES1_IP_PAYLOAD_UNKNOWN 0x0
> #define RDES1_IP_PAYLOAD_UDP 0x1
>
On my Elkhart system, i cannot use dwqe0
"Intel Elkhart Lake LH2OSE" rev 0x11 at pci0 dev 29 function 0 not configured
dwqe0 at pci0 dev 29 function 1 "Intel Elkhart Lake Ethernet" rev
0x11: rev 0x52, address ff:ff:ff:ff:ff:ff
eephy0 at dwqe0 phy 1: 88E1512 10/100/1000 PHY, rev. 1
"Intel Elkhart Lake Ethernet" rev 0x11 at pci0 dev 29 function 2 not configured
"Intel Elkhart Lake UART" rev 0x11 at pci0 dev 30 function 0 not configured
"Intel Elkhart Lake Ethernet" rev 0x11 at pci0 dev 30 function 4 not configured
I dig into the drivers a bit and i think linux ignores dwqe0 and
directly declare two eephy0
I would test more patches around Elkhart support but it's not working.
I m not sure why the driver that are extremely similar diverge so much
on that point, i think the relevant part is over here
https://github.com/openbsd/src/blob/master/sys/dev/pci/if_em_hw.c#L211
while most other system ( FreeBSD etc , separated most of it in 'e1000' )
https://github.com/torvalds/linux/blob/master/drivers/net/ethernet/intel/igb/e1000_phy.c#L2198
To support this 88E1512 ( the two optical drivers hidden behind the
dwqe0 ) , is it just a matter of ids and missing initialisation
in if_em_hw ? or does the all intel driver need a massive overall ?
Best.
Linux stuff:
[ 46.819061] Intel(R) 2.5G Ethernet Linux Driver
[ 46.819070] Copyright(c) 2018 Intel Corporation.
[ 46.819119] igc 0000:01:00.0: enabling device (0000 -> 0002)
[ 46.819306] igc 0000:01:00.0: PCIe PTM not supported by PCIe bus/controller
[ 46.865255] pps pps0: new PPS source ptp0
[ 46.865383] igc 0000:01:00.0 (unnamed net_device) (uninitialized): PHC added
[ 46.889042] igc 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth
(5.0 GT/s PCIe x1 link)
[ 46.889052] igc 0000:01:00.0 eth0: MAC: 68:ed:a4:47:74:cc
[ 46.889378] igc 0000:02:00.0: enabling device (0000 -> 0002)
[ 46.889569] igc 0000:02:00.0: PCIe PTM not supported by PCIe bus/controller
[ 46.914264] intel-eth-pci 0000:00:1d.1: enabling device (0000 -> 0002)
[ 46.915054] intel-eth-pci 0000:00:1d.1: stmmac_config_multi_msi:
multi MSI enablement successful
[ 46.915150] intel-eth-pci 0000:00:1d.1: User ID: 0x51, Synopsys ID: 0x52
[ 46.915158] intel-eth-pci 0000:00:1d.1: DWMAC4/5
[ 46.915167] intel-eth-pci 0000:00:1d.1: DMA HW capability register supported
[ 46.915169] intel-eth-pci 0000:00:1d.1: RX Checksum Offload Engine supported
[ 46.915171] intel-eth-pci 0000:00:1d.1: TX Checksum insertion supported
[ 46.915173] intel-eth-pci 0000:00:1d.1: TSO supported
[ 46.915175] intel-eth-pci 0000:00:1d.1: Enable RX Mitigation via HW
Watchdog Timer
[ 46.915183] intel-eth-pci 0000:00:1d.1: device MAC address 62:41:75:82:4b:00
[ 46.915186] intel-eth-pci 0000:00:1d.1: Enabled L3L4 Flow TC (entries=2)
[ 46.915188] intel-eth-pci 0000:00:1d.1: Enabled RFS Flow TC (entries=10)
[ 46.915194] intel-eth-pci 0000:00:1d.1: Enabling HW TC
(entries=256, max_off=256)
[ 46.915196] intel-eth-pci 0000:00:1d.1: TSO feature enabled
[ 46.915199] intel-eth-pci 0000:00:1d.1: Using 32/40 bits DMA
host/device width
[ 46.939061] pps pps1: new PPS source ptp1
[ 46.939124] igc 0000:02:00.0 (unnamed net_device) (uninitialized): PHC added
[ 46.964243] igc 0000:02:00.0: 4.000 Gb/s available PCIe bandwidth
(5.0 GT/s PCIe x1 link)
[ 46.964248] igc 0000:02:00.0 eth1: MAC: 68:ed:a4:47:74:cd
[ 46.964298] igc 0000:03:00.0: enabling device (0000 -> 0002)
[ 46.964483] igc 0000:03:00.0: PCIe PTM not supported by PCIe bus/controller
[ 47.012918] pps pps2: new PPS source ptp2
[ 47.012968] igc 0000:03:00.0 (unnamed net_device) (uninitialized): PHC added
[ 47.036979] igc 0000:03:00.0: 4.000 Gb/s available PCIe bandwidth
(5.0 GT/s PCIe x1 link)
[ 47.036985] igc 0000:03:00.0 eth2: MAC: 68:ed:a4:47:74:ce
[ 47.037032] igc 0000:04:00.0: enabling device (0000 -> 0002)
[ 47.037150] igc 0000:04:00.0: PCIe PTM not supported by PCIe bus/controller
[ 47.087033] pps pps3: new PPS source ptp3
[ 47.087082] igc 0000:04:00.0 (unnamed net_device) (uninitialized): PHC added
[ 47.104935] igc 0000:04:00.0: 4.000 Gb/s available PCIe bandwidth
(5.0 GT/s PCIe x1 link)
[ 47.104940] igc 0000:04:00.0 eth3: MAC: 68:ed:a4:47:74:cf
[ 47.104982] igc 0000:05:00.0: enabling device (0000 -> 0002)
[ 47.105087] igc 0000:05:00.0: PCIe PTM not supported by PCIe bus/controller
[ 47.134118] Marvell 88E1510 stmmac-2:01: attached PHY driver
(mii_bus:phy_addr=stmmac-2:01, irq=POLL)
[ 47.134443] intel-eth-pci 0000:00:1d.2: enabling device (0000 -> 0002)
[ 47.135096] intel-eth-pci 0000:00:1d.2: stmmac_config_multi_msi:
multi MSI enablement successful
[ 47.135193] intel-eth-pci 0000:00:1d.2: User ID: 0x51, Synopsys ID: 0x52
[ 47.135201] intel-eth-pci 0000:00:1d.2: DWMAC4/5
[ 47.135210] intel-eth-pci 0000:00:1d.2: DMA HW capability register supported
[ 47.135212] intel-eth-pci 0000:00:1d.2: RX Checksum Offload Engine supported
[ 47.135213] intel-eth-pci 0000:00:1d.2: TX Checksum insertion supported
[ 47.135214] intel-eth-pci 0000:00:1d.2: TSO supported
[ 47.135216] intel-eth-pci 0000:00:1d.2: Enable RX Mitigation via HW
Watchdog Timer
[ 47.135221] intel-eth-pci 0000:00:1d.2: device MAC address 4a:66:00:91:ca:47
[ 47.135224] intel-eth-pci 0000:00:1d.2: Enabled L3L4 Flow TC (entries=2)
[ 47.135226] intel-eth-pci 0000:00:1d.2: Enabled RFS Flow TC (entries=10)
[ 47.135232] intel-eth-pci 0000:00:1d.2: Enabling HW TC
(entries=256, max_off=256)
[ 47.135234] intel-eth-pci 0000:00:1d.2: TSO feature enabled
[ 47.135236] intel-eth-pci 0000:00:1d.2: Using 32/40 bits DMA
host/device width
[ 47.155063] pps pps4: new PPS source ptp4
[ 47.155118] igc 0000:05:00.0 (unnamed net_device) (uninitialized): PHC added
[ 47.179837] igc 0000:05:00.0: 4.000 Gb/s available PCIe bandwidth
(5.0 GT/s PCIe x1 link)
[ 47.179842] igc 0000:05:00.0 eth5: MAC: 68:ed:a4:47:74:d0
[ 47.341688] Marvell 88E1510 stmmac-3:01: attached PHY driver
(mii_bus:phy_addr=stmmac-3:01, irq=POLL)
[ 47.342112] intel-eth-pci 0000:00:1e.4: enabling device (0000 -> 0002)
[ 47.342891] intel-eth-pci 0000:00:1e.4: stmmac_config_multi_msi:
multi MSI enablement successful
[ 47.342981] intel-eth-pci 0000:00:1e.4: User ID: 0x51, Synopsys ID: 0x52
[ 47.342985] intel-eth-pci 0000:00:1e.4: DWMAC4/5
[ 47.342992] intel-eth-pci 0000:00:1e.4: DMA HW capability register supported
[ 47.342994] intel-eth-pci 0000:00:1e.4: RX Checksum Offload Engine supported
[ 47.342996] intel-eth-pci 0000:00:1e.4: TX Checksum insertion supported
[ 47.342997] intel-eth-pci 0000:00:1e.4: TSO supported
[ 47.342999] intel-eth-pci 0000:00:1e.4: Enable RX Mitigation via HW
Watchdog Timer
[ 47.343004] intel-eth-pci 0000:00:1e.4: device MAC address fa:84:21:87:c0:6d
[ 47.343007] intel-eth-pci 0000:00:1e.4: Enabled L3L4 Flow TC (entries=2)
[ 47.343009] intel-eth-pci 0000:00:1e.4: Enabled RFS Flow TC (entries=10)
[ 47.343014] intel-eth-pci 0000:00:1e.4: Enabling HW TC
(entries=256, max_off=256)
[ 47.343017] intel-eth-pci 0000:00:1e.4: TSO feature enabled
[ 47.343019] intel-eth-pci 0000:00:1e.4: Using 40/40 bits DMA
host/device width
[ 47.548526] Marvell 88E1510 stmmac-1:01: attached PHY driver
(mii_bus:phy_addr=stmmac-1:01, irq=POLL)
[ 49.552415] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-0
[ 49.553377] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-1
[ 49.554318] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-2
[ 49.555273] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-3
[ 49.556226] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-4
[ 49.557185] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-5
[ 49.558117] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-6
[ 49.559062] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-7
[ 49.621805] intel-eth-pci 0000:00:1d.1 eth4: PHY [stmmac-2:01]
driver [Marvell 88E1510] (irq=POLL)
[ 49.628712] dwmac4: Master AXI performs any burst length
[ 49.628793] intel-eth-pci 0000:00:1d.1 eth4: Enabling Safety Features
[ 49.628839] intel-eth-pci 0000:00:1d.1 eth4: IEEE 1588-2008
Advanced Timestamp supported
[ 49.628965] intel-eth-pci 0000:00:1d.1 eth4: registered PTP clock
[ 49.629111] intel-eth-pci 0000:00:1d.1 eth4: FPE workqueue start
[ 49.629115] intel-eth-pci 0000:00:1d.1 eth4: configuring for
phy/rgmii-id link mode
[ 49.638763] intel-eth-pci 0000:00:1d.1 eth4: FPE workqueue stop
[ 49.720456] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-0
[ 49.721326] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-1
[ 49.722173] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-2
[ 49.723035] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-3
[ 49.723880] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-4
[ 49.724745] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-5
[ 49.725600] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-6
[ 49.726445] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-7
[ 49.789806] intel-eth-pci 0000:00:1d.2 eth6: PHY [stmmac-3:01]
driver [Marvell 88E1510] (irq=POLL)
[ 49.796712] dwmac4: Master AXI performs any burst length
[ 49.796791] intel-eth-pci 0000:00:1d.2 eth6: Enabling Safety Features
[ 49.796836] intel-eth-pci 0000:00:1d.2 eth6: IEEE 1588-2008
Advanced Timestamp supported
[ 49.796953] intel-eth-pci 0000:00:1d.2 eth6: registered PTP clock
[ 49.797100] intel-eth-pci 0000:00:1d.2 eth6: FPE workqueue start
[ 49.797104] intel-eth-pci 0000:00:1d.2 eth6: configuring for
phy/rgmii-id link mode
[ 49.806733] intel-eth-pci 0000:00:1d.2 eth6: FPE workqueue stop
[ 49.809689] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-0
[ 49.810646] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-1
[ 49.811598] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-2
[ 49.812545] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-3
[ 49.813522] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-4
[ 49.814459] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-5
[ 49.815416] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-6
[ 49.816360] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-7
[ 49.881813] intel-eth-pci 0000:00:1e.4 eth7: PHY [stmmac-1:01]
driver [Marvell 88E1510] (irq=POLL)
[ 49.893816] dwmac4: Master AXI performs any burst length
[ 49.893901] intel-eth-pci 0000:00:1e.4 eth7: Enabling Safety Features
[ 49.903889] intel-eth-pci 0000:00:1e.4 eth7: IEEE 1588-2008
Advanced Timestamp supported
[ 49.903999] intel-eth-pci 0000:00:1e.4 eth7: registered PTP clock
[ 49.904137] intel-eth-pci 0000:00:1e.4 eth7: FPE workqueue start
[ 49.904140] intel-eth-pci 0000:00:1e.4 eth7: configuring for
inband/sgmii link mode
[ 49.915079] intel-eth-pci 0000:00:1e.4 eth7: FPE workqueue stop
[ 63.628006] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-0
[ 63.628884] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-1
[ 63.629726] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-2
[ 63.630584] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-3
[ 63.631447] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-4
[ 63.632306] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-5
[ 63.633187] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-6
[ 63.634048] intel-eth-pci 0000:00:1d.1 eth4: Register
MEM_TYPE_PAGE_POOL RxQ-7
[ 63.698022] intel-eth-pci 0000:00:1d.1 eth4: PHY [stmmac-2:01]
driver [Marvell 88E1510] (irq=POLL)
[ 63.704711] dwmac4: Master AXI performs any burst length
[ 63.704792] intel-eth-pci 0000:00:1d.1 eth4: Enabling Safety Features
[ 63.704838] intel-eth-pci 0000:00:1d.1 eth4: IEEE 1588-2008
Advanced Timestamp supported
[ 63.704954] intel-eth-pci 0000:00:1d.1 eth4: registered PTP clock
[ 63.705107] intel-eth-pci 0000:00:1d.1 eth4: FPE workqueue start
[ 63.705111] intel-eth-pci 0000:00:1d.1 eth4: configuring for
phy/rgmii-id link mode
[ 66.715579] intel-eth-pci 0000:00:1d.1 eth4: FPE workqueue stop
[ 69.797830] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-0
[ 69.798680] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-1
[ 69.799536] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-2
[ 69.800400] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-3
[ 69.801289] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-4
[ 69.802135] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-5
[ 69.802993] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-6
[ 69.803859] intel-eth-pci 0000:00:1d.2 eth6: Register
MEM_TYPE_PAGE_POOL RxQ-7
[ 69.866018] intel-eth-pci 0000:00:1d.2 eth6: PHY [stmmac-3:01]
driver [Marvell 88E1510] (irq=POLL)
[ 69.872711] dwmac4: Master AXI performs any burst length
[ 69.872790] intel-eth-pci 0000:00:1d.2 eth6: Enabling Safety Features
[ 69.872835] intel-eth-pci 0000:00:1d.2 eth6: IEEE 1588-2008
Advanced Timestamp supported
[ 69.872959] intel-eth-pci 0000:00:1d.2 eth6: registered PTP clock
[ 69.873113] intel-eth-pci 0000:00:1d.2 eth6: FPE workqueue start
[ 69.873117] intel-eth-pci 0000:00:1d.2 eth6: configuring for
phy/rgmii-id link mode
[ 72.883635] intel-eth-pci 0000:00:1d.2 eth6: FPE workqueue stop
[ 72.883940] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-0
[ 72.884873] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-1
[ 72.885840] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-2
[ 72.886749] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-3
[ 72.887676] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-4
[ 72.888575] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-5
[ 72.889508] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-6
[ 72.890384] intel-eth-pci 0000:00:1e.4 eth7: Register
MEM_TYPE_PAGE_POOL RxQ-7
[ 72.954028] intel-eth-pci 0000:00:1e.4 eth7: PHY [stmmac-1:01]
driver [Marvell 88E1510] (irq=POLL)
[ 72.964711] dwmac4: Master AXI performs any burst length
[ 72.964793] intel-eth-pci 0000:00:1e.4 eth7: Enabling Safety Features
[ 72.974782] intel-eth-pci 0000:00:1e.4 eth7: IEEE 1588-2008
Advanced Timestamp supported
[ 72.974888] intel-eth-pci 0000:00:1e.4 eth7: registered PTP clock
[ 72.975034] intel-eth-pci 0000:00:1e.4 eth7: FPE workqueue start
[ 72.975038] intel-eth-pci 0000:00:1e.4 eth7: configuring for
inband/sgmii link mode
[ 75.987786] intel-eth-pci 0000:00:1e.4 eth7: FPE workqueue stop
[ 234.557120] igc 0000:01:00.0 eth0: NIC Link is Up 1000 Mbps Full
Duplex, Flow Control: RX/TX
OpenBSD
"Intel Elkhart Lake I2C" rev 0x11 at pci0 dev 27 function 0 not configured
"Intel Elkhart Lake I2C" rev 0x11 at pci0 dev 27 function 1 not configured
"Intel Elkhart Lake I2C" rev 0x11 at pci0 dev 27 function 6 not configured
ppb0 at pci0 dev 28 function 0 "Intel Elkhart Lake PCIE" rev 0x11: msi
pci1 at ppb0 bus 1
igc0 at pci1 dev 0 function 0 "Intel I225-V" rev 0x03, msix, 4 queues,
address 68:ed:a4:47:74:cc
ppb1 at pci0 dev 28 function 1 "Intel Elkhart Lake PCIE" rev 0x11: msi
pci2 at ppb1 bus 2
igc1 at pci2 dev 0 function 0 "Intel I225-V" rev 0x03, msix, 4 queues,
address 68:ed:a4:47:74:cd
ppb2 at pci0 dev 28 function 2 "Intel Elkhart Lake PCIE" rev 0x11: msi
pci3 at ppb2 bus 3
igc2 at pci3 dev 0 function 0 "Intel I225-V" rev 0x03, msix, 4 queues,
address 68:ed:a4:47:74:ce
ppb3 at pci0 dev 28 function 3 "Intel Elkhart Lake PCIE" rev 0x11: msi
pci4 at ppb3 bus 4
igc3 at pci4 dev 0 function 0 "Intel I225-V" rev 0x03, msix, 4 queues,
address 68:ed:a4:47:74:cf
ppb4 at pci0 dev 28 function 6 "Intel Elkhart Lake PCIE" rev 0x11: msi
pci5 at ppb4 bus 5
igc4 at pci5 dev 0 function 0 "Intel I225-V" rev 0x03, msix, 4 queues,
address 68:ed:a4:47:74:d0
"Intel Elkhart Lake LH2OSE" rev 0x11 at pci0 dev 29 function 0 not configured
dwqe0 at pci0 dev 29 function 1 "Intel Elkhart Lake Ethernet" rev
0x11: rev 0x52, address ff:ff:ff:ff:ff:ff
eephy0 at dwqe0 phy 1: 88E1512 10/100/1000 PHY, rev. 1
"Intel Elkhart Lake Ethernet" rev 0x11 at pci0 dev 29 function 2 not configured
"Intel Elkhart Lake UART" rev 0x11 at pci0 dev 30 function 0 not configured
"Intel Elkhart Lake Ethernet" rev 0x11 at pci0 dev 30 function 4 not configured
Thank you for reading that far.
dwqe(4) VLAN offload