The patch below populates arm64 hwcaps from the ID_AA64ISAR0 register.

I didn't look at other registers and I don't know if we want to do
it this way.  There is the question of keeping this in sync with
the CPU_ID_AA64* sysctl() for filtering out unsupported options.

It's intended as a provisional change to signal the common AES,
SHA, CRC32 instruction extensions via elf_aux_info(), so people can
check how that interacts with ports.

-----------------------------------------------
commit ebba40aebdc3568b1e6bc72a492f8d8b7fb3e1a3 (local)
from: Christian Weisgerber <naddy@mips.inka.de>
date: Tue Jul 16 20:02:15 2024 UTC
 
 arm64: provisionally populate hwcaps with ID_AA64ISAR0 register
 
diff 9982db7b2eb53fd996e16d3eea6e03b5353a2d91 ebba40aebdc3568b1e6bc72a492f8d8b7fb3e1a3
commit - 9982db7b2eb53fd996e16d3eea6e03b5353a2d91
commit + ebba40aebdc3568b1e6bc72a492f8d8b7fb3e1a3
blob - 69898059074417a146f80b96d4afe6d29bf354ae
blob + a1b35356ea69053870e6beee361a2738885ba9b6
--- sys/arch/arm64/arm64/cpu.c
+++ sys/arch/arm64/arm64/cpu.c
@@ -692,6 +692,7 @@ cpu_identify(struct cpu_info *ci)
 		printf("%sRNDR", sep);
 		sep = ",";
 		arm64_has_rng = 1;
+		hwcap2 |= HWCAP2_RNG;
 	}
 
 	if (ID_AA64ISAR0_TLB(id) >= ID_AA64ISAR0_TLB_IOS) {
@@ -704,38 +705,47 @@ cpu_identify(struct cpu_info *ci)
 	if (ID_AA64ISAR0_TS(id) >= ID_AA64ISAR0_TS_BASE) {
 		printf("%sTS", sep);
 		sep = ",";
+		hwcap |= HWCAP_FLAGM;
 	}
-	if (ID_AA64ISAR0_TS(id) >= ID_AA64ISAR0_TS_AXFLAG)
+	if (ID_AA64ISAR0_TS(id) >= ID_AA64ISAR0_TS_AXFLAG) {
 		printf("+AXFLAG");
+		hwcap2 |= HWCAP2_FLAGM2;
+	}
 
 	if (ID_AA64ISAR0_FHM(id) >= ID_AA64ISAR0_FHM_IMPL) {
 		printf("%sFHM", sep);
 		sep = ",";
+		hwcap |= HWCAP_ASIMDFHM;
 	}
 
 	if (ID_AA64ISAR0_DP(id) >= ID_AA64ISAR0_DP_IMPL) {
 		printf("%sDP", sep);
 		sep = ",";
+		hwcap |= HWCAP_ASIMDDP;
 	}
 
 	if (ID_AA64ISAR0_SM4(id) >= ID_AA64ISAR0_SM4_IMPL) {
 		printf("%sSM4", sep);
 		sep = ",";
+		hwcap |= HWCAP_SM4;
 	}
 
 	if (ID_AA64ISAR0_SM3(id) >= ID_AA64ISAR0_SM3_IMPL) {
 		printf("%sSM3", sep);
 		sep = ",";
+		hwcap |= HWCAP_SM3;
 	}
 
 	if (ID_AA64ISAR0_SHA3(id) >= ID_AA64ISAR0_SHA3_IMPL) {
 		printf("%sSHA3", sep);
 		sep = ",";
+		hwcap |= HWCAP_SHA3;
 	}
 
 	if (ID_AA64ISAR0_RDM(id) >= ID_AA64ISAR0_RDM_IMPL) {
 		printf("%sRDM", sep);
 		sep = ",";
+		hwcap |= HWCAP_ASIMDRDM;
 	}
 
 	if (ID_AA64ISAR0_ATOMIC(id) >= ID_AA64ISAR0_ATOMIC_IMPL) {
@@ -751,18 +761,23 @@ cpu_identify(struct cpu_info *ci)
 	if (ID_AA64ISAR0_CRC32(id) >= ID_AA64ISAR0_CRC32_BASE) {
 		printf("%sCRC32", sep);
 		sep = ",";
+		hwcap |= HWCAP_CRC32;
 	}
 
 	if (ID_AA64ISAR0_SHA2(id) >= ID_AA64ISAR0_SHA2_BASE) {
 		printf("%sSHA2", sep);
 		sep = ",";
+		hwcap |= HWCAP_SHA2;
 	}
-	if (ID_AA64ISAR0_SHA2(id) >= ID_AA64ISAR0_SHA2_512)
+	if (ID_AA64ISAR0_SHA2(id) >= ID_AA64ISAR0_SHA2_512) {
 		printf("+SHA512");
+		hwcap |= HWCAP_SHA512;
+	}
 
 	if (ID_AA64ISAR0_SHA1(id) >= ID_AA64ISAR0_SHA1_BASE) {
 		printf("%sSHA1", sep);
 		sep = ",";
+		hwcap |= HWCAP_SHA1;
 	}
 
 	if (ID_AA64ISAR0_AES(id) >= ID_AA64ISAR0_AES_BASE) {
@@ -771,9 +786,12 @@ cpu_identify(struct cpu_info *ci)
 #ifdef CRYPTO
 		arm64_has_aes = 1;
 #endif
+		hwcap |= HWCAP_AES;
 	}
-	if (ID_AA64ISAR0_AES(id) >= ID_AA64ISAR0_AES_PMULL)
+	if (ID_AA64ISAR0_AES(id) >= ID_AA64ISAR0_AES_PMULL) {
 		printf("+PMULL");
+		hwcap |= HWCAP_PMULL;
+	}
 
 	/*
 	 * ID_AA64ISAR1

-- 
Christian "naddy" Weisgerber                          naddy@mips.inka.de