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More arm64 hwcap
This pretty much completes populating hwcap and hwcap2 on arm64.
Still need to look into what's up with HWCAP_EVSTRM.
I think Linux added a few more HWCAP2_xxx defines that FreeBSD didn't
pick up yet. But let's pause here for a bit; the current list already
includes features not available in any commercially available
hardware.
ok?
Index: arch/arm64/arm64/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/arm64/arm64/cpu.c,v
retrieving revision 1.130
diff -u -p -r1.130 cpu.c
--- arch/arm64/arm64/cpu.c 24 Jul 2024 21:24:18 -0000 1.130
+++ arch/arm64/arm64/cpu.c 26 Jul 2024 14:13:11 -0000
@@ -884,17 +884,49 @@ cpu_identify(struct cpu_info *ci)
printf("%sDPB", sep);
sep = ",";
}
+ if (ID_AA64ISAR1_DPB(id) >= ID_AA64ISAR1_DPB_DCCVADP)
+ printf("+DCCVADP");
/*
* ID_AA64ISAR2
*/
id = READ_SPECIALREG(id_aa64isar2_el1);
+ if (ID_AA64ISAR2_CSSC(id) >= ID_AA64ISAR2_CSSC_IMPL) {
+ printf("%sBC", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR2_RPRFM(id) >= ID_AA64ISAR2_RPRFM_IMPL) {
+ printf("%sRPRFM", sep);
+ sep = ",";
+ }
+
if (ID_AA64ISAR2_CLRBHB(id) >= ID_AA64ISAR2_CLRBHB_IMPL) {
printf("%sCLRBHB", sep);
sep = ",";
}
+ if (ID_AA64ISAR2_BC(id) >= ID_AA64ISAR2_BC_IMPL) {
+ printf("%sBC", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR2_MOPS(id) >= ID_AA64ISAR2_MOPS_IMPL) {
+ printf("%sMOPS", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR2_RPRES(id) >= ID_AA64ISAR2_RPRES_IMPL) {
+ printf("%sRPRES", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64ISAR2_WFXT(id) >= ID_AA64ISAR2_WFXT_IMPL) {
+ printf("%sWFXT", sep);
+ sep = ",";
+ }
+
/*
* ID_AA64MMFR0
*
@@ -902,6 +934,13 @@ cpu_identify(struct cpu_info *ci)
*/
id = READ_SPECIALREG(id_aa64mmfr0_el1);
+ if (ID_AA64MMFR0_ECV(id) >= ID_AA64MMFR0_ECV_IMPL) {
+ printf("%sECV", sep);
+ sep = ",";
+ }
+ if (ID_AA64MMFR0_ECV(id) >= ID_AA64MMFR0_ECV_CNTHCTL)
+ printf("+CNTHCTL");
+
if (ID_AA64MMFR0_ASID_BITS(id) == ID_AA64MMFR0_ASID_BITS_16) {
printf("%sASID16", sep);
sep = ",";
@@ -914,6 +953,11 @@ cpu_identify(struct cpu_info *ci)
*/
id = READ_SPECIALREG(id_aa64mmfr1_el1);
+ if (ID_AA64MMFR1_AFP(id) >= ID_AA64MMFR1_AFP_IMPL) {
+ printf("%sAFP", sep);
+ sep = ",";
+ }
+
if (ID_AA64MMFR1_SPECSEI(id) >= ID_AA64MMFR1_SPECSEI_IMPL) {
printf("%sSpecSEI", sep);
sep = ",";
@@ -965,6 +1009,11 @@ cpu_identify(struct cpu_info *ci)
sep = ",";
}
+ if (ID_AA64MMFR2_AT(id) >= ID_AA64MMFR2_AT_IMPL) {
+ printf("%sAT", sep);
+ sep = ",";
+ }
+
/*
* ID_AA64PFR0
*/
@@ -989,6 +1038,18 @@ cpu_identify(struct cpu_info *ci)
sep = ",";
}
+ if (ID_AA64PFR0_ADV_SIMD(id) != ID_AA64PFR0_ADV_SIMD_NONE &&
+ ID_AA64PFR0_ADV_SIMD(id) >= ID_AA64PFR0_ADV_SIMD_HP) {
+ printf("%sAdvSIMD+HP", sep);
+ sep = ",";
+ }
+
+ if (ID_AA64PFR0_FP(id) != ID_AA64PFR0_FP_NONE &&
+ ID_AA64PFR0_FP(id) >= ID_AA64PFR0_FP_HP) {
+ printf("%sFP+HP", sep);
+ sep = ",";
+ }
+
/*
* ID_AA64PFR1
*/
@@ -1070,13 +1131,19 @@ cpu_identify_cleanup(void)
cpu_id_aa64isar2 = value;
/* ID_AA64MMFR0_EL1 */
- cpu_id_aa64mmfr0 = 0;
+ value = 0;
+ value |= cpu_id_aa64mmfr0 & ID_AA64MMFR0_ECV_MASK;
+ cpu_id_aa64mmfr0 = value;
/* ID_AA64MMFR1_EL1 */
- cpu_id_aa64mmfr1 = 0;
+ value = 0;
+ value |= cpu_id_aa64mmfr1 & ID_AA64MMFR1_AFP_MASK;
+ cpu_id_aa64mmfr1 = value;
/* ID_AA64MMFR2_EL1 */
- cpu_id_aa64mmfr2 = 0;
+ value = 0;
+ value |= cpu_id_aa64mmfr2 & ID_AA64MMFR2_AT_MASK;
+ cpu_id_aa64mmfr2 = value;
/* ID_AA64PFR0_EL1 */
value = 0;
@@ -1107,8 +1174,12 @@ cpu_identify_cleanup(void)
hwcap |= HWCAP_CRC32;
if (ID_AA64ISAR0_ATOMIC(cpu_id_aa64isar0) >= ID_AA64ISAR0_ATOMIC_IMPL)
hwcap |= HWCAP_ATOMICS;
- /* HWCAP_FPHP */
- /* HWCAP_ASIMDHP */
+ if (ID_AA64PFR0_FP(cpu_id_aa64pfr0) != ID_AA64PFR0_FP_NONE &&
+ ID_AA64PFR0_FP(cpu_id_aa64pfr0) >= ID_AA64PFR0_FP_HP)
+ hwcap |= HWCAP_FPHP;
+ if (ID_AA64PFR0_FP(cpu_id_aa64pfr0) != ID_AA64PFR0_ADV_SIMD_NONE &&
+ ID_AA64PFR0_FP(cpu_id_aa64pfr0) >= ID_AA64PFR0_ADV_SIMD_HP)
+ hwcap |= HWCAP_ASIMDHP;
id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
if (ID_AA64MMFR2_IDS(id_aa64mmfr2) >= ID_AA64MMFR2_IDS_IMPL)
hwcap |= HWCAP_CPUID;
@@ -1137,7 +1208,8 @@ cpu_identify_cleanup(void)
hwcap |= HWCAP_ASIMDFHM;
if (ID_AA64PFR0_DIT(cpu_id_aa64pfr0) >= ID_AA64PFR0_DIT_IMPL)
hwcap |= HWCAP_DIT;
- /* HWCAP_USCAT */
+ if (ID_AA64MMFR2_AT(cpu_id_aa64mmfr2) >= ID_AA64MMFR2_AT_IMPL)
+ hwcap |= HWCAP_USCAT;
if (ID_AA64ISAR1_LRCPC(cpu_id_aa64isar1) >= ID_AA64ISAR1_LRCPC_LDAPUR)
hwcap |= HWCAP_ILRCPC;
if (ID_AA64ISAR0_TS(cpu_id_aa64isar0) >= ID_AA64ISAR0_TS_BASE)
@@ -1154,7 +1226,8 @@ cpu_identify_cleanup(void)
hwcap |= HWCAP_PACG;
/* HWCAP2 */
- /* HWCAP2_DCPODP */
+ if (ID_AA64ISAR1_DPB(cpu_id_aa64isar1) >= ID_AA64ISAR1_DPB_DCCVADP)
+ hwcap2 |= HWCAP2_DCPODP;
/* HWCAP2_SVE2: OpenBSD kernel doesn't provide SVE support */
/* HWCAP2_SVEAES: OpenBSD kernel doesn't provide SVE support */
/* HWCAP2_SVEPMULL: OpenBSD kernel doesn't provide SVE support */
@@ -1180,9 +1253,12 @@ cpu_identify_cleanup(void)
if (ID_AA64PFR1_BT(cpu_id_aa64pfr1) >= ID_AA64PFR1_BT_IMPL)
hwcap2 |= HWCAP2_BTI;
/* HWCAP2_MTE: OpenBSD kernel doesn't provide MTE support */
- /* HWCAP2_ECV */
- /* HWCAP2_AFP */
- /* HWCAP2_RPRES */
+ if (ID_AA64MMFR0_ECV(cpu_id_aa64mmfr0) >= ID_AA64MMFR0_ECV_IMPL)
+ hwcap2 |= HWCAP2_ECV;
+ if (ID_AA64MMFR1_AFP(cpu_id_aa64mmfr1) >= ID_AA64MMFR1_AFP_IMPL)
+ hwcap2 |= HWCAP2_AFP;
+ if (ID_AA64ISAR2_RPRES(cpu_id_aa64isar2) >= ID_AA64ISAR2_RPRES_IMPL)
+ hwcap2 |= HWCAP2_RPRES;
/* HWCAP2_MTE3: OpenBSD kernel doesn't provide MTE support */
/* HWCAP2_SME: OpenBSD kernel doesn't provide SME support */
/* HWCAP2_SME_I16I64: OpenBSD kernel doesn't provide SME support */
@@ -1192,12 +1268,15 @@ cpu_identify_cleanup(void)
/* HWCAP2_SME_B16F32: OpenBSD kernel doesn't provide SME support */
/* HWCAP2_SME_F32F32: OpenBSD kernel doesn't provide SME support */
/* HWCAP2_SME_FA64: OpenBSD kernel doesn't provide SME support */
- /* HWCAP2_WFXT */
+ if (ID_AA64ISAR2_WFXT(cpu_id_aa64isar2) >= ID_AA64ISAR2_WFXT_IMPL)
+ hwcap2 |= HWCAP2_WFXT;
if (ID_AA64ISAR1_BF16(cpu_id_aa64isar1) >= ID_AA64ISAR1_BF16_EBF)
hwcap2 |= HWCAP2_EBF16;
/* HWCAP2_SVE_EBF16: OpenBSD kernel doesn't provide SVE support */
- /* HWCAP2_CSSC */
- /* HWCAP2_RPRFM */
+ if (ID_AA64ISAR2_CSSC(cpu_id_aa64isar2) >= ID_AA64ISAR2_CSSC_IMPL)
+ hwcap2 |= HWCAP2_CSSC;
+ if (ID_AA64ISAR2_RPRFM(cpu_id_aa64isar2) >= ID_AA64ISAR2_RPRFM_IMPL)
+ hwcap2 |= HWCAP2_RPRFM;
/* HWCAP2_SVE2P1: OpenBSD kernel doesn't provide SVE support */
/* HWCAP2_SME2: OpenBSD kernel doesn't provide SME support */
/* HWCAP2_SME2P1: OpenBSD kernel doesn't provide SME support */
@@ -1205,8 +1284,10 @@ cpu_identify_cleanup(void)
/* HWCAP2_SME_BI32I32: OpenBSD kernel doesn't provide SME support */
/* HWCAP2_SME_B16B16: OpenBSD kernel doesn't provide SME support */
/* HWCAP2_SME_F16F16: OpenBSD kernel doesn't provide SME support */
- /* HWCAP2_MOPS */
- /* HWCAP2_HBC */
+ if (ID_AA64ISAR2_MOPS(cpu_id_aa64isar2) >= ID_AA64ISAR2_MOPS_IMPL)
+ hwcap2 |= HWCAP2_MOPS;
+ if (ID_AA64ISAR2_BC(cpu_id_aa64isar2) >= ID_AA64ISAR2_BC_IMPL)
+ hwcap2 |= HWCAP2_HBC;
}
void cpu_init(void);
Index: arch/arm64/include/armreg.h
===================================================================
RCS file: /cvs/src/sys/arch/arm64/include/armreg.h,v
retrieving revision 1.36
diff -u -p -r1.36 armreg.h
--- arch/arm64/include/armreg.h 24 Jul 2024 21:24:18 -0000 1.36
+++ arch/arm64/include/armreg.h 26 Jul 2024 14:13:11 -0000
@@ -363,6 +363,7 @@
#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (0x0ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_IMPL (0x1ULL << ID_AA64ISAR1_DPB_SHIFT)
+#define ID_AA64ISAR1_DPB_DCCVADP (0x2ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_APA_SHIFT 4
#define ID_AA64ISAR1_APA_MASK (0xfULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK)
@@ -446,15 +447,45 @@
#define ID_AA64ISAR1_LS64_ACCDATA (0x3ULL << ID_AA64ISAR1_LS64_SHIFT)
/* ID_AA64ISAR2_EL1 */
-#define ID_AA64ISAR2_MASK 0x00000000f0000000ULL
+#define ID_AA64ISAR2_MASK 0x00ff0000f0ff00ffULL
+#define ID_AA64ISAR2_WFXT_SHIFT 0
+#define ID_AA64ISAR2_WFXT_MASK (0xfULL << ID_AA64ISAR2_WFXT_SHIFT)
+#define ID_AA64ISAR2_WFXT(x) ((x) & ID_AA64ISAR2_WFXT_MASK)
+#define ID_AA64ISAR2_WFXT_NONE (0x0ULL << ID_AA64ISAR2_WFXT_SHIFT)
+#define ID_AA64ISAR2_WFXT_IMPL (0x2ULL << ID_AA64ISAR2_WFXT_SHIFT)
+#define ID_AA64ISAR2_RPRES_SHIFT 4
+#define ID_AA64ISAR2_RPRES_MASK (0xfULL << ID_AA64ISAR2_RPRES_SHIFT)
+#define ID_AA64ISAR2_RPRES(x) ((x) & ID_AA64ISAR2_RPRES_MASK)
+#define ID_AA64ISAR2_RPRES_NONE (0x0ULL << ID_AA64ISAR2_RPRES_SHIFT)
+#define ID_AA64ISAR2_RPRES_IMPL (0x1ULL << ID_AA64ISAR2_RPRES_SHIFT)
+#define ID_AA64ISAR2_MOPS_SHIFT 16
+#define ID_AA64ISAR2_MOPS_MASK (0xfULL << ID_AA64ISAR2_MOPS_SHIFT)
+#define ID_AA64ISAR2_MOPS(x) ((x) & ID_AA64ISAR2_MOPS_MASK)
+#define ID_AA64ISAR2_MOPS_NONE (0x0ULL << ID_AA64ISAR2_MOPS_SHIFT)
+#define ID_AA64ISAR2_MOPS_IMPL (0x1ULL << ID_AA64ISAR2_MOPS_SHIFT)
+#define ID_AA64ISAR2_BC_SHIFT 20
+#define ID_AA64ISAR2_BC_MASK (0xfULL << ID_AA64ISAR2_BC_SHIFT)
+#define ID_AA64ISAR2_BC(x) ((x) & ID_AA64ISAR2_BC_MASK)
+#define ID_AA64ISAR2_BC_NONE (0x0ULL << ID_AA64ISAR2_BC_SHIFT)
+#define ID_AA64ISAR2_BC_IMPL (0x1ULL << ID_AA64ISAR2_BC_SHIFT)
#define ID_AA64ISAR2_CLRBHB_SHIFT 28
#define ID_AA64ISAR2_CLRBHB_MASK (0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_CLRBHB(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK)
#define ID_AA64ISAR2_CLRBHB_NONE (0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_CLRBHB_IMPL (0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
+#define ID_AA64ISAR2_RPRFM_SHIFT 48
+#define ID_AA64ISAR2_RPRFM_MASK (0xfULL << ID_AA64ISAR2_RPRFM_SHIFT)
+#define ID_AA64ISAR2_RPRFM(x) ((x) & ID_AA64ISAR2_RPRFM_MASK)
+#define ID_AA64ISAR2_RPRFM_NONE (0x0ULL << ID_AA64ISAR2_RPRFM_SHIFT)
+#define ID_AA64ISAR2_RPRFM_IMPL (0x1ULL << ID_AA64ISAR2_RPRFM_SHIFT)
+#define ID_AA64ISAR2_CSSC_SHIFT 52
+#define ID_AA64ISAR2_CSSC_MASK (0xfULL << ID_AA64ISAR2_CSSC_SHIFT)
+#define ID_AA64ISAR2_CSSC(x) ((x) & ID_AA64ISAR2_CSSC_MASK)
+#define ID_AA64ISAR2_CSSC_NONE (0x0ULL << ID_AA64ISAR2_CSSC_SHIFT)
+#define ID_AA64ISAR2_CSSC_IMPL (0x1ULL << ID_AA64ISAR2_CSSC_SHIFT)
/* ID_AA64MMFR0_EL1 */
-#define ID_AA64MMFR0_MASK 0x00000000ffffffffULL
+#define ID_AA64MMFR0_MASK 0xf0000000ffffffffULL
#define ID_AA64MMFR0_PA_RANGE_SHIFT 0
#define ID_AA64MMFR0_PA_RANGE_MASK (0xfULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK)
@@ -499,9 +530,15 @@
#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK)
#define ID_AA64MMFR0_TGRAN4_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_TGRAN4_NONE (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT)
+#define ID_AA64MMFR0_ECV_SHIFT 60
+#define ID_AA64MMFR0_ECV_MASK (0xfULL << ID_AA64MMFR0_ECV_SHIFT)
+#define ID_AA64MMFR0_ECV(x) ((x) & ID_AA64MMFR0_ECV_MASK)
+#define ID_AA64MMFR0_ECV_NONE (0x0ULL << ID_AA64MMFR0_ECV_SHIFT)
+#define ID_AA64MMFR0_ECV_IMPL (0x1ULL << ID_AA64MMFR0_ECV_SHIFT)
+#define ID_AA64MMFR0_ECV_CNTHCTL (0x2ULL << ID_AA64MMFR0_ECV_SHIFT)
/* ID_AA64MMFR1_EL1 */
-#define ID_AA64MMFR1_MASK 0xf0000000ffffffffULL
+#define ID_AA64MMFR1_MASK 0xf000f000ffffffffULL
#define ID_AA64MMFR1_HAFDBS_SHIFT 0
#define ID_AA64MMFR1_HAFDBS_MASK (0xfULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
@@ -545,6 +582,11 @@
#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK)
#define ID_AA64MMFR1_XNX_NONE (0x0ULL << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_XNX_IMPL (0x1ULL << ID_AA64MMFR1_XNX_SHIFT)
+#define ID_AA64MMFR1_AFP_SHIFT 44
+#define ID_AA64MMFR1_AFP_MASK (0xfULL << ID_AA64MMFR1_AFP_SHIFT)
+#define ID_AA64MMFR1_AFP(x) ((x) & ID_AA64MMFR1_AFP_MASK)
+#define ID_AA64MMFR1_AFP_NONE (0x0ULL << ID_AA64MMFR1_AFP_SHIFT)
+#define ID_AA64MMFR1_AFP_IMPL (0x1ULL << ID_AA64MMFR1_AFP_SHIFT)
#define ID_AA64MMFR1_ECBHB_SHIFT 60
#define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT)
#define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK)
@@ -557,9 +599,15 @@
#define ID_AA64MMFR2_CCIDX_MASK (0xfULL << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
#define ID_AA64MMFR2_CCIDX_IMPL (0x1ULL << ID_AA64MMFR2_CCIDX_SHIFT)
+#define ID_AA64MMFR2_AT_SHIFT 32
+#define ID_AA64MMFR2_AT_MASK (0xfULL << ID_AA64MMFR2_AT_SHIFT)
+#define ID_AA64MMFR2_AT(x) ((x) & ID_AA64MMFR2_AT_MASK)
+#define ID_AA64MMFR2_AT_NONE (0x0ULL << ID_AA64MMFR2_AT_SHIFT)
+#define ID_AA64MMFR2_AT_IMPL (0x1ULL << ID_AA64MMFR2_AT_SHIFT)
#define ID_AA64MMFR2_IDS_SHIFT 36
#define ID_AA64MMFR2_IDS_MASK (0xfULL << ID_AA64MMFR2_IDS_SHIFT)
#define ID_AA64MMFR2_IDS(x) ((x) & ID_AA64MMFR2_IDS_MASK)
+#define ID_AA64MMFR2_IDS_NONE (0x0ULL << ID_AA64MMFR2_IDS_SHIFT)
#define ID_AA64MMFR2_IDS_IMPL (0x1ULL << ID_AA64MMFR2_IDS_SHIFT)
/* ID_AA64PFR0_EL1 */
@@ -590,11 +638,13 @@
#define ID_AA64PFR0_FP_MASK (0xfULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK)
#define ID_AA64PFR0_FP_IMPL (0x0ULL << ID_AA64PFR0_FP_SHIFT)
+#define ID_AA64PFR0_FP_HP (0x1ULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP_NONE (0xfULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_SHIFT 20
#define ID_AA64PFR0_ADV_SIMD_MASK (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK)
#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0ULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
+#define ID_AA64PFR0_ADV_SIMD_HP (0x1ULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_NONE (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */
#define ID_AA64PFR0_GIC_SHIFT 24
More arm64 hwcap