Hello,

I'm commiting ixv(4) from NAITO Yuichiro.  Almost of the changes can
be done separately from ix(4), but the diff bellow is the part which
actually affect ix(4).

ok?

Expose {T,R}X desc trail and add link_enabled field to prepare VF
support.

Index: sys/dev/pci/if_ix.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_ix.c,v
diff -u -p -u -p -r1.216 if_ix.c
--- sys/dev/pci/if_ix.c	31 Aug 2024 16:23:09 -0000	1.216
+++ sys/dev/pci/if_ix.c	2 Sep 2024 04:01:51 -0000
@@ -508,7 +508,7 @@ ixgbe_start(struct ifqueue *ifq)
 	 * hardware that this frame is available to transmit.
 	 */
 	if (post)
-		IXGBE_WRITE_REG(&sc->hw, IXGBE_TDT(txr->me),
+		IXGBE_WRITE_REG(&sc->hw, txr->tail,
 		    txr->next_avail_desc);
 }
 
@@ -706,7 +706,7 @@ ixgbe_watchdog(struct ifnet * ifp)
 	for (i = 0; i < sc->num_queues; i++, txr++) {
 		printf("%s: Queue(%d) tdh = %d, hw tdt = %d\n", ifp->if_xname, i,
 		    IXGBE_READ_REG(hw, IXGBE_TDH(i)),
-		    IXGBE_READ_REG(hw, IXGBE_TDT(i)));
+		    IXGBE_READ_REG(hw, sc->tx_rings[i].tail));
 		printf("%s: TX(%d) Next TX to Clean = %d\n", ifp->if_xname,
 		    i, txr->next_to_clean);
 	}
@@ -826,7 +826,7 @@ ixgbe_init(void *arg)
 				msec_delay(1);
 		}
 		IXGBE_WRITE_FLUSH(&sc->hw);
-		IXGBE_WRITE_REG(&sc->hw, IXGBE_RDT(i), rxr->last_desc_filled);
+		IXGBE_WRITE_REG(&sc->hw, rxr[i].tail, rxr->last_desc_filled);
 	}
 
 	/* Set up VLAN support and filter */
@@ -2365,9 +2365,12 @@ ixgbe_initialize_transmit_units(struct i
 		IXGBE_WRITE_REG(hw, IXGBE_TDLEN(i),
 		    sc->num_tx_desc * sizeof(struct ixgbe_legacy_tx_desc));
 
+		/* Set Tx Tail register */
+		txr->tail = IXGBE_TDT(i);
+
 		/* Setup the HW Tx Head and Tail descriptor pointers */
 		IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_TDT(i), 0);
+		IXGBE_WRITE_REG(hw, txr->tail, 0);
 
 		/* Setup Transmit Descriptor Cmd Settings */
 		txr->txd_cmd = IXGBE_TXD_CMD_IFCS;
@@ -2844,7 +2847,7 @@ ixgbe_rxrefill(void *xrxr)
 
 	if (ixgbe_rxfill(rxr)) {
 		/* Advance the Rx Queue "Tail Pointer" */
-		IXGBE_WRITE_REG(&sc->hw, IXGBE_RDT(rxr->me),
+		IXGBE_WRITE_REG(&sc->hw, rxr->tail,
 		    rxr->last_desc_filled);
 	} else if (if_rxr_inuse(&rxr->rx_ring) == 0)
 		timeout_add(&rxr->rx_refill, 1);
@@ -2940,6 +2943,9 @@ ixgbe_initialize_receive_units(struct ix
 		srrctl = bufsz | IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
 		IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(i), srrctl);
 
+		/* Capture Rx Tail index */
+		rxr->tail = IXGBE_RDT(i);
+
 		if (ISSET(ifp->if_xflags, IFXF_LRO)) {
 			rdrxctl = IXGBE_READ_REG(&sc->hw, IXGBE_RSCCTL(i));
 
@@ -2952,7 +2958,7 @@ ixgbe_initialize_receive_units(struct ix
 
 		/* Setup the HW Rx Head and Tail Descriptor Pointers */
 		IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
+		IXGBE_WRITE_REG(hw, rxr->tail, 0);
 	}
 
 	if (sc->hw.mac.type != ixgbe_mac_82598EB) {
Index: sys/dev/pci/if_ix.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_ix.h,v
diff -u -p -u -p -r1.47 if_ix.h
--- sys/dev/pci/if_ix.h	21 May 2024 11:19:39 -0000	1.47
+++ sys/dev/pci/if_ix.h	2 Sep 2024 04:01:51 -0000
@@ -169,6 +169,7 @@ struct ix_txring {
 	struct ix_softc		*sc;
 	struct ifqueue		*ifq;
 	uint32_t		me;
+	uint32_t		tail;
 	uint32_t		watchdog_timer;
 	union ixgbe_adv_tx_desc	*tx_base;
 	struct ixgbe_tx_buf	*tx_buffers;
@@ -194,6 +195,7 @@ struct ix_rxring {
 	struct ix_softc		*sc;
 	struct ifiqueue		*ifiq;
 	uint32_t		me;
+	uint32_t		tail;
 	union ixgbe_adv_rx_desc	*rx_base;
 	struct ixgbe_dma_alloc	rxdma;
 #if 0
@@ -244,6 +246,7 @@ struct ix_softc {
 	uint16_t		num_segs;
 	uint32_t		link_speed;
 	bool			link_up;
+	bool			link_enabled;
 	uint32_t		linkvec;
 	struct rwlock		sfflock;