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support MediaTek interrupt controller
On Sat, Jan 25, 2025 at 10:29:45PM +0100, Mark Kettenis wrote:
> > From: James Hastings <moosetek4@gmail.com>
> > Date: Sat, 25 Jan 2025 15:21:54 -0500 (EST)
> >
> > Add support for MediaTek system interrupt controller.
> >
> > This controller is the default interrupt-parent on older design SoCs.
> > It is located upstream from GIC and sole function is interrupt
> > polarity control.
> >
> > ramdisk console log below.
> >
> > ok?
>
> We tend to give interrupt controllers names that end in "intc", so
> mtintc(4) would perhaps be better. Patrick, how do you feel about
> that.
I also think mtintc(4) would be a better fit. And I checked the DTSs,
I don't think Mediatek has another interrupt controller that the name
could clash with in the future. Otherwise, looks good as well.
> I'm always a bit hesitant to add suspend/resume support to drivers
> before that can be really tested. But in this case the implementation
> is probably right.
>
> Otherwise this looks good.
>
>
> > Index: sys/dev/fdt/mtsysirq.c
> > ===================================================================
> > RCS file: sys/dev/fdt/mtsysirq.c
> > diff -N sys/dev/fdt/mtsysirq.c
> > --- /dev/null 1 Jan 1970 00:00:00 -0000
> > +++ sys/dev/fdt/mtsysirq.c 23 Jan 2025 23:17:04 -0000
> > @@ -0,0 +1,145 @@
> > +/* $OpenBSD$ */
> > +/*
> > + * Copyright (c) 2025 James Hastings <hastings@openbsd.org>
> > + *
> > + * Permission to use, copy, modify, and distribute this software for any
> > + * purpose with or without fee is hereby granted, provided that the above
> > + * copyright notice and this permission notice appear in all copies.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> > + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> > + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> > + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> > + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> > + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> > + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> > + */
> > +
> > +#include <sys/param.h>
> > +#include <sys/device.h>
> > +#include <sys/malloc.h>
> > +#include <sys/systm.h>
> > +
> > +#include <machine/bus.h>
> > +#include <machine/fdt.h>
> > +#include <machine/intr.h>
> > +
> > +#include <dev/ofw/openfirm.h>
> > +#include <dev/ofw/fdt.h>
> > +
> > +struct mtsysirq_softc {
> > + struct device sc_dev;
> > + bus_space_tag_t sc_iot;
> > + bus_space_handle_t sc_ioh;
> > + bus_size_t sc_ios;
> > +
> > + int sc_nirq;
> > + uint32_t *sc_irq_cfg;
> > +
> > + struct interrupt_controller sc_ic;
> > +};
> > +
> > +int mtsysirq_match(struct device *, void *, void *);
> > +void mtsysirq_attach(struct device *, struct device *, void *);
> > +int mtsysirq_activate(struct device *, int);
> > +
> > +void *mtsysirq_establish_fdt(void *, int *, int, struct cpu_info *,
> > + int (*)(void *), void *, char *);
> > +
> > +const struct cfattach mtsysirq_ca = {
> > + sizeof(struct mtsysirq_softc), mtsysirq_match, mtsysirq_attach, NULL,
> > + mtsysirq_activate
> > +};
> > +
> > +struct cfdriver mtsysirq_cd = {
> > + NULL, "mtsysirq", DV_DULL
> > +};
> > +
> > +int
> > +mtsysirq_match(struct device *parent, void *match, void *aux)
> > +{
> > + struct fdt_attach_args *faa = aux;
> > +
> > + return OF_is_compatible(faa->fa_node, "mediatek,mt6577-sysirq");
> > +}
> > +
> > +void
> > +mtsysirq_attach(struct device *parent, struct device *self, void *aux)
> > +{
> > + struct mtsysirq_softc *sc = (struct mtsysirq_softc *)self;
> > + struct fdt_attach_args *faa = aux;
> > +
> > + if (faa->fa_nreg < 1) {
> > + printf(": no registers\n");
> > + return;
> > + }
> > +
> > + sc->sc_iot = faa->fa_iot;
> > + sc->sc_ios = faa->fa_reg[0].size;
> > + if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
> > + sc->sc_ios, 0, &sc->sc_ioh))
> > + panic("%s: bus_space_map failed!", __func__);
> > +
> > + sc->sc_nirq = sc->sc_ios * 8;
> > + sc->sc_irq_cfg = malloc(sc->sc_ios, M_DEVBUF, M_WAITOK);
> > +
> > + sc->sc_ic.ic_node = faa->fa_node;
> > + sc->sc_ic.ic_cookie = sc;
> > + sc->sc_ic.ic_establish = mtsysirq_establish_fdt;
> > +
> > + printf(" nirq %d\n", sc->sc_nirq);
> > +
> > + fdt_intr_register(&sc->sc_ic);
> > +}
> > +
> > +int
> > +mtsysirq_activate(struct device *self, int act)
> > +{
> > + struct mtsysirq_softc *sc = (struct mtsysirq_softc *)self;
> > +
> > + switch (act) {
> > + case DVACT_SUSPEND:
> > + bus_space_read_region_4(sc->sc_iot, sc->sc_ioh, 0,
> > + sc->sc_irq_cfg, sc->sc_ios / sizeof(uint32_t));
> > + break;
> > + case DVACT_RESUME:
> > + bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, 0,
> > + sc->sc_irq_cfg, sc->sc_ios / sizeof(uint32_t));
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +void
> > +mtsysirq_invert(struct mtsysirq_softc *sc, int irq)
> > +{
> > + int reg = (irq / 32) * 4;
> > + int bit = (irq % 32);
> > +
> > + bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg,
> > + bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) | 1U << bit);
> > +}
> > +
> > +void *
> > +mtsysirq_establish_fdt(void *cookie, int *cells, int level,
> > + struct cpu_info *ci, int (*func)(void *), void *arg, char *name)
> > +{
> > + struct mtsysirq_softc *sc = cookie;
> > + int irq = cells[1];
> > + int flags = cells[2];
> > +
> > + KASSERT(cells[0] == 0);
> > + KASSERT(irq >= 0 && irq < sc->sc_nirq);
> > +
> > +#ifdef DEBUG_INTC
> > + printf("%s: irq %d level %d flags 0x%x [%s]\n", __func__, irq, level,
> > + flags, name);
> > +#endif
> > +
> > + if (flags & 0xa)
> > + mtsysirq_invert(sc, irq);
> > +
> > + return fdt_intr_parent_establish(&sc->sc_ic, cells, level, ci, func,
> > + arg, name);
> > +}
> > Index: sys/dev/fdt/files.fdt
> > ===================================================================
> > RCS file: /cvs/src/sys/dev/fdt/files.fdt,v
> > retrieving revision 1.204
> > diff -u -p -r1.204 files.fdt
> > --- sys/dev/fdt/files.fdt 16 Nov 2024 21:17:54 -0000 1.204
> > +++ sys/dev/fdt/files.fdt 23 Jan 2025 23:17:04 -0000
> > @@ -336,6 +336,10 @@ device hitemp
> > attach hitemp at fdt
> > file dev/fdt/hitemp.c hitemp
> >
> > +device mtsysirq
> > +attach mtsysirq at fdt
> > +file dev/fdt/mtsysirq.c mtsysirq
> > +
> > device rkanxdp
> > attach rkanxdp at fdt
> > file dev/fdt/rkanxdp.c rkanxdp
> > Index: share/man/man4/mtsysirq.4
> > ===================================================================
> > RCS file: share/man/man4/mtsysirq.4
> > diff -N share/man/man4/mtsysirq.4
> > --- /dev/null 1 Jan 1970 00:00:00 -0000
> > +++ share/man/man4/mtsysirq.4 23 Jan 2025 23:17:04 -0000
> > @@ -0,0 +1,46 @@
> > +.\" $OpenBSD$
> > +.\"
> > +.\" Copyright (c) 2025 James Hastings <hastings@openbsd.org>
> > +.\"
> > +.\" Permission to use, copy, modify, and distribute this software for any
> > +.\" purpose with or without fee is hereby granted, provided that the above
> > +.\" copyright notice and this permission notice appear in all copies.
> > +.\"
> > +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> > +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> > +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> > +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> > +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> > +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> > +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> > +.\"
> > +.Dd $Mdocdate$
> > +.Dt MTSYSIRQ 4
> > +.Os
> > +.Sh NAME
> > +.Nm mtsysirq
> > +.Nd MediaTek system interrupt controller
> > +.Sh SYNOPSIS
> > +.Cd "mtsysirq* at fdt?"
> > +.Sh DESCRIPTION
> > +The
> > +.Nm
> > +driver provides support for the system interrupt controller
> > +integrated on MediaTek SoCs.
> > +The controller provides per-interrupt polarity inversion
> > +and transparent forwarding to an
> > +Arm Generic Interrupt Controller (GIC).
> > +.Sh SEE ALSO
> > +.Xr intro 4 ,
> > +.Xr ampintc 4
> > +.Sh HISTORY
> > +The
> > +.Nm
> > +driver first appeared in
> > +.Ox 7.7 .
> > +.Sh AUTHORS
> > +.An -nosplit
> > +The
> > +.Nm
> > +driver was written by
> > +.An James Hastings Aq Mt hastings@openbsd.org .
> > Index: share/man/man4/Makefile
> > ===================================================================
> > RCS file: /cvs/src/share/man/man4/Makefile,v
> > retrieving revision 1.857
> > diff -u -p -r1.857 Makefile
> > --- share/man/man4/Makefile 15 Dec 2024 11:07:08 -0000 1.857
> > +++ share/man/man4/Makefile 23 Jan 2025 23:17:04 -0000
> > @@ -58,7 +58,8 @@ MAN= aac.4 abcrtc.4 abl.4 ac97.4 acphy.4
> > maestro.4 mainbus.4 malo.4 maxds.4 maxrtc.4 maxtmp.4 mbg.4 \
> > mcprtc.4 mcx.4 midi.4 mii.4 mfi.4 mfii.4 mfokrtc.4 \
> > mlphy.4 moscom.4 mos.4 mpe.4 mpath.4 mpi.4 mpii.4 \
> > - mpip.4 mpu.4 msk.4 mpw.4 msts.4 mtd.4 mtdphy.4 mtio.4 mtw.4 mue.4 \
> > + mpip.4 mpu.4 msk.4 mpw.4 msts.4 mtd.4 mtdphy.4 mtio.4 \
> > + mtsysirq.4 mtw.4 mue.4 \
> > multicast.4 mvclock.4 mvdog.4 mvgicp.4 mvgpio.4 mvicu.4 mviic.4 \
> > mvkpcie.4 mvneta.4 mvpinctrl.4 mvpp.4 mvrng.4 mvrtc.4 mvspi.4 \
> > mvtemp.4 mvsw.4 mvuart.4 myx.4 \
> > Index: sys/arch/arm64/conf/GENERIC
> > ===================================================================
> > RCS file: /cvs/src/sys/arch/arm64/conf/GENERIC,v
> > retrieving revision 1.290
> > diff -u -p -r1.290 GENERIC
> > --- sys/arch/arm64/conf/GENERIC 17 Nov 2024 16:35:05 -0000 1.290
> > +++ sys/arch/arm64/conf/GENERIC 23 Jan 2025 23:17:04 -0000
> > @@ -272,6 +272,9 @@ hidwusb* at fdt?
> > hireset* at fdt? early 1
> > hitemp* at fdt?
> >
> > +# MediaTek SoCs
> > +mtsysirq* at fdt?
> > +
> > # Marvell SoCs
> > mvclock* at fdt? early 1
> > mvgicp* at fdt? early 1
> > Index: sys/arch/arm64/conf/RAMDISK
> > ===================================================================
> > RCS file: /cvs/src/sys/arch/arm64/conf/RAMDISK,v
> > retrieving revision 1.219
> > diff -u -p -r1.219 RAMDISK
> > --- sys/arch/arm64/conf/RAMDISK 14 Aug 2024 14:40:46 -0000 1.219
> > +++ sys/arch/arm64/conf/RAMDISK 23 Jan 2025 23:17:04 -0000
> > @@ -204,6 +204,9 @@ hiclock* at fdt? early 1
> > hidwusb* at fdt?
> > hireset* at fdt? early 1
> >
> > +# MediaTek SoCs
> > +mtsysirq* at fdt?
> > +
> > # Marvell SoCs
> > mvclock* at fdt? early 1
> > mvgicp* at fdt? early 1
> > Index: sys/arch/armv7/conf/GENERIC
> > ===================================================================
> > RCS file: /cvs/src/sys/arch/armv7/conf/GENERIC,v
> > retrieving revision 1.142
> > diff -u -p -r1.142 GENERIC
> > --- sys/arch/armv7/conf/GENERIC 12 Mar 2023 10:50:06 -0000 1.142
> > +++ sys/arch/armv7/conf/GENERIC 23 Jan 2025 23:17:04 -0000
> > @@ -184,6 +184,9 @@ bcmtemp* at fdt?
> > dwctwo* at fdt?
> > usb* at dwctwo?
> >
> > +# MediaTek SoCs
> > +mtsysirq* at fdt?
> > +
> > # Marvell SoC
> > mvacc* at fdt? early 1
> > mvagc* at fdt?
> > Index: sys/arch/armv7/conf/RAMDISK
> > ===================================================================
> > RCS file: /cvs/src/sys/arch/armv7/conf/RAMDISK,v
> > retrieving revision 1.130
> > diff -u -p -r1.130 RAMDISK
> > --- sys/arch/armv7/conf/RAMDISK 2 Mar 2023 09:59:29 -0000 1.130
> > +++ sys/arch/armv7/conf/RAMDISK 23 Jan 2025 23:17:05 -0000
> > @@ -170,6 +170,9 @@ sdmmc* at bcmsdhost?
> > dwctwo* at fdt?
> > usb* at dwctwo?
> >
> > +# MediaTek SoCs
> > +mtsysirq* at fdt?
> > +
> > # Marvell SoC
> > mvacc* at fdt? early 1
> > mvagc* at fdt?
> >
> >
> > console log:
> > F0: 102B 0000
> > F5: 0000 0000
> > V0: 0000 0000 [0001]
> > 00: 0000 0000
> > BP: 0400 0041 [0000]
> > G0: 1190 0000
> > T0: 0000 0295 [000F]
> > Jump to BL
> >
> > NOTICE: BL2: v2.10.0 (release):OpenWrt v2024.01.17~bacca82a-3 (mt7622-sdmmc-2ddr)
> > NOTICE: BL2: Built : 19:52:54, Jan 22 2025
> > NOTICE: WDT: [40000000] Software reset (reboot)
> > NOTICE: CPU: MT7622
> > NOTICE: BL2: Booting BL31
> > NOTICE: BL31: v2.10.0 (release):OpenWrt v2024.01.17~bacca82a-3 (mt7622-sdmmc-2ddr)
> > NOTICE: BL31: Built : 19:52:54, Jan 22 2025
> >
> >
> > U-Boot 2024.10-OpenWrt-r28388-58d0057481 (Jan 22 2025 - 19:52:54 +0000)
> >
> > CPU: MediaTek MT7622
> > Model: mt7622-bpi-r64
> > DRAM: 1 GiB
> > Core: 68 devices, 26 uclasses, devicetree: separate
> > MMC: mmc@11230000: 0, mmc@11240000: 1
> > Loading Environment from MMC... Reading from MMC(1)... OK
> > In: serial@11002000
> > Out: serial@11002000
> > Err: serial@11002000
> > reset button found
> > Loading Environment from MMC... Reading from MMC(1)... OK
> > Net: eth0: ethernet@1b100000
> > MT7622> dhcp bootaa64.efi
> > BOOTP broadcast 1
> > BOOTP broadcast 2
> > BOOTP broadcast 3
> > DHCP client bound to address
> > Using ethernet@1b100000 device
> > TFTP from server
> > Filename 'bootaa64.efi'.
> > Load address: 0x48000000
> > Loading: *################
> > 4.2 MiB/s
> > done
> > Bytes transferred = 233390 (38fae hex)
> > MT7622> tftpboot 0x47000000 mt7622-bpi-r64.dtb
> > Using ethernet@1b100000 device
> > TFTP from server
> > Filename 'mt7622-bpi-r64.dtb'.
> > Load address: 0x47000000
> > Loading: *##
> > 4.1 MiB/s
> > done
> > Bytes transferred = 26006 (6596 hex)
> > MT7622> bootefi 0x48000000 0x47000000
> > Cannot read EFI system partition
> > Cannot read EFI system partition
> > Failed to persist EFI variables
> > Booting /bootaa64.efi
> > disks: sd0 sd1
> > >> OpenBSD/arm64 BOOTAA64 1.20
> > boot> bsd
> > booting tftp0a:bsd ...
> > Copyright (c) 1982, 1986, 1989, 1991, 1993
> > The Regents of the University of California. All rights reserved.
> > Copyright (c) 1995-2025 OpenBSD. All rights reserved. https://www.OpenBSD.org
> >
> > OpenBSD 7.6-current (RAMDISK) #5: Thu Jan 23 18:38:19 EST 2025
> > hastings@rpi4a.moose-tek.test:/usr/src/sys/arch/arm64/compile/RAMDISK
> > real mem = 1071976448 (1022MB)
> > avail mem = 998469632 (952MB)
> > random: good seed from bootblocks
> > mainbus0 at root: Bananapi BPI-R64
> > psci0 at mainbus0: PSCI 1.1, SMCCC 1.4, SYSTEM_SUSPEND
> > efi0 at mainbus0: UEFI 2.10
> > efi0: Das U-Boot rev 0x20241000
> > smbios0 at efi0: SMBIOS 3.7.0
> > smbios0: vendor U-Boot version "2024.10-OpenWrt-r28388-58d0057481" date 10/01/2024
> > smbios0: mediatek mt7622-bpi-r64
> > cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4
> > cpu0: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
> > cpu0: 256KB 64b/line 16-way L2 cache
> > cpu0: CRC32,SHA2,SHA1,AES+PMULL,ASID16
> > "ramoops" at mainbus0 not configured
> > "secmon" at mainbus0 not configured
> > syscon0 at mainbus0: "infracfg"
> > syscon1 at mainbus0: "pericfg"
> > syscon2 at mainbus0: "power-controller"
> > ampintc0 at mainbus0 nirq 288, ncpu 4: "interrupt-controller"
> > syscon3 at mainbus0: "clock-controller"
> > syscon4 at mainbus0: "pciecfg"
> > syscon5 at mainbus0: "clock-controller"
> > syscon6 at mainbus0: "pcie-mirror"
> > syscon7 at mainbus0: "wed"
> > syscon8 at mainbus0: "wed"
> > syscon9 at mainbus0: "sgmiisys"
> > "opp-table" at mainbus0 not configured
> > "dummy40m" at mainbus0 not configured
> > "oscillator" at mainbus0 not configured
> > "pmu" at mainbus0 not configured
> > agtimer0 at mainbus0: 12500 kHz
> > "pwrap" at mainbus0 not configured
> > "ir-receiver" at mainbus0 not configured
> > mtsysirq0 at mainbus0 nirq 256
> > "efuse" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "rng" at mainbus0 not configured
> > "pinctrl" at mainbus0 not configured
> > "watchdog" at mainbus0 not configured
> > "rtc" at mainbus0 not configured
> > "cci" at mainbus0 not configured
> > "adc" at mainbus0 not configured
> > com0 at mainbus0: ns16550a, 16 byte fifo
> > com0: console
> > "pwm" at mainbus0 not configured
> > "i2c" at mainbus0 not configured
> > "i2c" at mainbus0 not configured
> > "spi" at mainbus0 not configured
> > "thermal" at mainbus0 not configured
> > "serial" at mainbus0 not configured
> > "spi" at mainbus0 not configured
> > "ecc" at mainbus0 not configured
> > "mmc" at mainbus0 not configured
> > "mmc" at mainbus0 not configured
> > "wmac" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "usb" at mainbus0 not configured
> > "t-phy" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "pcie" at mainbus0 not configured
> > "pcie" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "dma-controller" at mainbus0 not configured
> > "ethernet" at mainbus0 not configured
> > "gpio-keys" at mainbus0 not configured
> > "leds" at mainbus0 not configured
> > "regulator-1p8v" at mainbus0 not configured
> > "regulator-3p3v" at mainbus0 not configured
> > "regulator-5v" at mainbus0 not configured
> > softraid0 at root
> > scsibus0 at softraid0: 256 targets
> > root on rd0a swap on rd0b dump on rd0b
> > WARNING: CHECK AND RESET THE DATE!
> > cpu0: clock not implemented
> > erase ^?, werase ^W, kill ^U, intr ^C, status ^T
> >
> > Welcome to the OpenBSD/arm64 7.6 installation program.
> > (I)nstall, (U)pgrade, (A)utoinstall or (S)hell? s
> > # sysctl
> > kern.osrelease=7.6
> > hw.machine=arm64
> > hw.model=ARM Cortex-A53 r0p4
> > hw.product=mt7622-bpi-r64
> > hw.disknames=rd0:43375a97a110a516
> > hw.ncpufound=2
> > machdep.compatible=bananapi,bpi-r64
> > # mount
> > /dev/rd0a on / type ffs (local)
> > # ifconfig
> > lo0: flags=2008008<LOOPBACK,MULTICAST,LRO> mtu 32768
> > llprio 3
> > groups: lo
> > # reboot
> > syncing disks... done
> > rebooting...
> >
> > F0: 102B 0000
> > F5: 0000 0000
> > V0: 0000 0000 [0001]
> > 00: 0000 0000
> > BP: 0400 0041 [0000]
> > G0: 1190 0000
> > T0: 0000 0294 [000F]
> > Jump to BL
> >
> > NOTICE: BL2: v2.10.0 (release):OpenWrt v2024.01.17~bacca82a-3 (mt7622-sdmmc-2ddr)
> > NOTICE: BL2: Built : 19:52:54, Jan 22 2025
> > NOTICE: WDT: [40000000] Software reset (reboot)
> > NOTICE: CPU: MT7622
> > NOTICE: BL2: Booting BL31
> > NOTICE: BL31: v2.10.0 (release):OpenWrt v2024.01.17~bacca82a-3 (mt7622-sdmmc-2ddr)
> > NOTICE: BL31: Built : 19:52:54, Jan 22 2025
> >
> >
> > U-Boot 2024.10-OpenWrt-r28388-58d0057481 (Jan 22 2025 - 19:52:54 +0000)
> >
> > CPU: MediaTek MT7622
> > Model: mt7622-bpi-r64
> > DRAM: 1 GiB
> > Core: 68 devices, 26 uclasses, devicetree: separate
> > MMC: mmc@11230000: 0, mmc@11240000: 1
> > Loading Environment from MMC... Reading from MMC(1)... OK
> > In: serial@11002000
> > Out: serial@11002000
> > Err: serial@11002000
> > reset button found
> > Loading Environment from MMC... Reading from MMC(1)... OK
> > Net: eth0: ethernet@1b100000
> > MT7622> dhcp bootaa64.efi
> >
> > BOOTP broadcast 1
> > DHCP client bound to address
> > Using ethernet@1b100000 device
> > TFTP from server
> > Filename 'bootaa64.efi'.
> > Load address: 0x48000000
> > Loading: *################
> > 4.2 MiB/s
> > done
> > Bytes transferred = 233390 (38fae hex)
> > MT7622> tftpboot 0x47000000 mt7622-bpi-r64.dtb
> > Using ethernet@1b100000 device
> > TFTP from server
> > Filename 'mt7622-bpi-r64.dtb'.
> > Load address: 0x47000000
> > Loading: *##
> > 4.1 MiB/s
> > done
> > Bytes transferred = 26006 (6596 hex)
> > MT7622> bootefi 0x48000000 0x47000000
> > Cannot read EFI system partition
> > Cannot read EFI system partition
> > Failed to persist EFI variables
> > Booting /bootaa64.efi
> > disks: sd0 sd1
> > >> OpenBSD/arm64 BOOTAA64 1.20
> > boot> bsd.7622
> > booting tftp0a:bsd.7622: ...
> > [ using 3072056 bytes of bsd ELF symbol table ]
> > Copyright (c) 1982, 1986, 1989, 1991, 1993
> > The Regents of the University of California. All rights reserved.
> > Copyright (c) 1995-2025 OpenBSD. All rights reserved. https://www.OpenBSD.org
> >
> > OpenBSD 7.6-current (GENERIC.MP) #0: Thu Jan 23 20:19:48 EST 2025
> > hastings@rpi4a.moose-tek.test:/usr/src/sys/arch/arm64/compile/GENERIC.MP
> > real mem = 1071976448 (1022MB)
> > avail mem = 998383616 (952MB)
> > random: good seed from bootblocks
> > mainbus0 at root: Bananapi BPI-R64
> > psci0 at mainbus0: PSCI 1.1, SMCCC 1.4, SYSTEM_SUSPEND
> > efi0 at mainbus0: UEFI 2.10
> > efi0: Das U-Boot rev 0x20241000
> > smbios0 at efi0: SMBIOS 3.7.0
> > smbios0: vendor U-Boot version "2024.10-OpenWrt-r28388-58d0057481" date 10/01/2024
> > smbios0: mediatek mt7622-bpi-r64
> > cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4
> > cpu0: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
> > cpu0: 256KB 64b/line 16-way L2 cache
> > cpu0: CRC32,SHA2,SHA1,AES+PMULL,ASID16
> > cpu1 at mainbus0 mpidr 1: ARM Cortex-A53 r0p4
> > cpu1: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
> > cpu1: 256KB 64b/line 16-way L2 cache
> > "ramoops" at mainbus0 not configured
> > "secmon" at mainbus0 not configured
> > apm0 at mainbus0
> > syscon0 at mainbus0: "infracfg"
> > syscon1 at mainbus0: "pericfg"
> > syscon2 at mainbus0: "power-controller"
> > ampintc0 at mainbus0 nirq 288, ncpu 4 ipi: 0, 1, 2: "interrupt-controller"
> > syscon3 at mainbus0: "clock-controller"
> > syscon4 at mainbus0: "pciecfg"
> > syscon5 at mainbus0: "clock-controller"
> > syscon6 at mainbus0: "pcie-mirror"
> > syscon7 at mainbus0: "wed"
> > syscon8 at mainbus0: "wed"
> > syscon9 at mainbus0: "sgmiisys"
> > "opp-table" at mainbus0 not configured
> > "dummy40m" at mainbus0 not configured
> > "oscillator" at mainbus0 not configured
> > "pmu" at mainbus0 not configured
> > agtimer0 at mainbus0: 12500 kHz
> > "pwrap" at mainbus0 not configured
> > "ir-receiver" at mainbus0 not configured
> > mtsysirq0 at mainbus0 nirq 256
> > "efuse" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "rng" at mainbus0 not configured
> > "pinctrl" at mainbus0 not configured
> > "watchdog" at mainbus0 not configured
> > "rtc" at mainbus0 not configured
> > "cci" at mainbus0 not configured
> > "adc" at mainbus0 not configured
> > com0 at mainbus0: ns16550a, 16 byte fifo
> > com0: console
> > "pwm" at mainbus0 not configured
> > "i2c" at mainbus0 not configured
> > "i2c" at mainbus0 not configured
> > "spi" at mainbus0 not configured
> > "thermal" at mainbus0 not configured
> > "serial" at mainbus0 not configured
> > "spi" at mainbus0 not configured
> > "ecc" at mainbus0 not configured
> > "mmc" at mainbus0 not configured
> > "mmc" at mainbus0 not configured
> > "wmac" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "usb" at mainbus0 not configured
> > "t-phy" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "pcie" at mainbus0 not configured
> > "pcie" at mainbus0 not configured
> > "clock-controller" at mainbus0 not configured
> > "dma-controller" at mainbus0 not configured
> > "ethernet" at mainbus0 not configured
> > gpiokeys0 at mainbus0: "factory", "wps"
> > gpioleds0 at mainbus0: "bpi-r64:pio:green", "bpi-r64:pio:red"
> > "regulator-1p8v" at mainbus0 not configured
> > "regulator-3p3v" at mainbus0 not configured
> > "regulator-5v" at mainbus0 not configured
> > vscsi0 at root
> > scsibus0 at vscsi0: 256 targets
> > softraid0 at root
> > scsibus1 at softraid0: 256 targets
> > root device:
> > use one of: exit
> > root device:
> > use one of: exit
> > root device: exit
> > syncing disks... done
> >
> >
support MediaTek interrupt controller