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rtwn_debug
Hello everyone. I was looking around and it seems like at the moment,
enabling "option RTWN_DEBUG" in the kernel config is pretty much
useless since the controlling variable in dev/ic/rtwn.c (rtwn_debug)
is set to 0 anyways.
Here is a diff to set it to 1 by default, which also simplifies
things a little bit, bringing it closer to code in other drivers
like bwi.
I actually have a urtwn device, and have verified that, at rtwn_debug=1,
this doesn't become excessively noisy. I respected most of the
behavior except in rtwn_iq_calib_run, where I bumped the debug level
by 1 to keep it less noisy.
Sounds good?
Index: dev/ic/rtwn.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/rtwn.c,v
diff -u -p -r1.59 rtwn.c
--- dev/ic/rtwn.c 20 Sep 2024 02:00:46 -0000 1.59
+++ dev/ic/rtwn.c 13 May 2025 00:27:39 -0000
@@ -82,12 +82,10 @@
#ifdef RTWN_DEBUG
-#define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0)
-#define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0)
-int rtwn_debug = 0;
+int rtwn_debug = 1;
+#define DPRINTF(l, x...) do { if (rtwn_debug >= (l)) printf(x); } while (0)
#else
-#define DPRINTF(x)
-#define DPRINTFN(n, x)
+#define DPRINTF(l, x...)
#endif
/* Registers to save and restore during IQ calibration. */
@@ -681,13 +679,13 @@ rtwn_r92c_read_rom(struct rtwn_softc *sc
/* XXX Weird but this is what the vendor driver does. */
sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa);
- DPRINTF(("PA setting=0x%x\n", sc->pa_setting));
+ DPRINTF(1, "PA setting=0x%x\n", sc->pa_setting);
sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
- DPRINTF(("board type=%d\n", sc->board_type));
+ DPRINTF(1, "board type=%d\n", sc->board_type);
sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
- DPRINTF(("regulatory type=%d\n", sc->regulatory));
+ DPRINTF(1, "regulatory type=%d\n", sc->regulatory);
IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr);
}
@@ -703,10 +701,10 @@ rtwn_r92e_read_rom(struct rtwn_softc *sc
sizeof(sc->sc_r92e_rom));
sc->crystal_cap = rom->xtal_k;
- DPRINTF(("crystal cap=0x%x\n", sc->crystal_cap));
+ DPRINTF(1, "crystal cap=0x%x\n", sc->crystal_cap);
sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY);
- DPRINTF(("regulatory type=%d\n", sc->regulatory));
+ DPRINTF(1, "regulatory type=%d\n", sc->regulatory);
IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr);
}
@@ -722,10 +720,10 @@ rtwn_r88e_read_rom(struct rtwn_softc *sc
sizeof(sc->sc_r88e_rom));
sc->crystal_cap = (sc->chip & RTWN_CHIP_PCI) ? 0x20 : rom->xtal;
- DPRINTF(("Crystal cap=0x%x\n", sc->crystal_cap));
+ DPRINTF(1, "Crystal cap=0x%x\n", sc->crystal_cap);
sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY);
- DPRINTF(("regulatory type=%d\n", sc->regulatory));
+ DPRINTF(1, "regulatory type=%d\n", sc->regulatory);
if (sc->chip & RTWN_CHIP_PCI)
IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->r88ee_rom.macaddr);
@@ -817,8 +815,8 @@ rtwn_ra_init(struct rtwn_softc *sc)
mode = R92C_RAID_11B;
else
mode = R92C_RAID_11BG;
- DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
- mode, rates, basicrates));
+ DPRINTF(1, "mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
+ mode, rates, basicrates);
if (sc->chip & RTWN_CHIP_PCI) {
/* Configure Automatic Rate Fallback Register. */
@@ -874,7 +872,7 @@ rtwn_r92c_ra_init(struct rtwn_softc *sc,
return (error);
}
/* Set initial MRR rate. */
- DPRINTF(("maxbasicrate=%d\n", maxbasicrate));
+ DPRINTF(1, "maxbasicrate=%d\n", maxbasicrate);
rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BC),
maxbasicrate);
@@ -888,7 +886,7 @@ rtwn_r92c_ra_init(struct rtwn_softc *sc,
return (error);
}
/* Set initial MRR rate. */
- DPRINTF(("maxrate=%d\n", maxrate));
+ DPRINTF(1, "maxrate=%d\n", maxrate);
rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BSS),
maxrate);
@@ -1015,7 +1013,7 @@ rtwn_calib(struct rtwn_softc *sc)
{
if (sc->avg_pwdb != -1) {
- DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb));
+ DPRINTF(3, "sending RSSI command avg=%d\n", sc->avg_pwdb);
/* Indicate Rx signal strength to FW for rate adaptation. */
if (sc->chip & RTWN_CHIP_92E) {
@@ -1068,9 +1066,9 @@ rtwn_newstate(struct ieee80211com *ic, e
ostate = ic->ic_state;
if (nstate != ostate)
- DPRINTF(("newstate %s -> %s\n",
+ DPRINTF(1, "newstate %s -> %s\n",
ieee80211_state_name[ostate],
- ieee80211_state_name[nstate]));
+ ieee80211_state_name[nstate]);
if (ostate == IEEE80211_S_RUN) {
/* Stop calibration. */
@@ -1447,7 +1445,7 @@ rtwn_update_avgrssi(struct rtwn_softc *s
sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
else
sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
- DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb));
+ DPRINTF(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb);
}
int8_t
@@ -1775,9 +1773,9 @@ rtwn_load_firmware(struct rtwn_softc *sc
(letoh16(hdr->signature) >> 4) == 0x88f ||
(letoh16(hdr->signature) >> 4) == 0x92c ||
(letoh16(hdr->signature) >> 4) == 0x92e) {
- DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n",
+ DPRINTF(1, "FW V%d.%d %02d-%02d %02d:%02d\n",
letoh16(hdr->version), letoh16(hdr->subversion),
- hdr->month, hdr->date, hdr->hour, hdr->minute));
+ hdr->month, hdr->date, hdr->hour, hdr->minute);
ptr += sizeof(*hdr);
len -= sizeof(*hdr);
}
@@ -2788,26 +2786,26 @@ rtwn_iq_calib_run(struct rtwn_softc *sc,
ret = rtwn_iq_calib_chain(sc, chain,
tx[chain], rx[chain]);
if (ret == 0) {
- DPRINTF(("%s: chain %d: Tx failed.\n",
- __func__, chain));
+ DPRINTF(2, "%s: chain %d: Tx failed.\n",
+ __func__, chain);
tx[chain][0] = 0xff;
tx[chain][1] = 0xff;
rx[chain][0] = 0xff;
rx[chain][1] = 0xff;
} else if (ret == 1) {
- DPRINTF(("%s: chain %d: Rx failed.\n",
- __func__, chain));
+ DPRINTF(2, "%s: chain %d: Rx failed.\n",
+ __func__, chain);
rx[chain][0] = 0xff;
rx[chain][1] = 0xff;
} else if (ret == 3) {
- DPRINTF(("%s: chain %d: Both Tx and Rx "
- "succeeded.\n", __func__, chain));
+ DPRINTF(2, "%s: chain %d: Both Tx and Rx "
+ "succeeded.\n", __func__, chain);
}
}
- DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, "
+ DPRINTF(2, "%s: results for run %d chain %d: tx[0]=0x%x, "
"tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain,
- tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]));
+ tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]);
}
rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00);
@@ -3070,7 +3068,7 @@ rtwn_temp_calib(struct rtwn_softc *sc)
temp = rtwn_rf_read(sc, 0, t_meter_reg) & 0x1f;
if (temp == 0) /* Read failed, skip. */
return;
- DPRINTFN(2, ("temperature=%d\n", temp));
+ DPRINTF(2, "temperature=%d\n", temp);
/*
* Redo IQ and LC calibration if temperature changed significantly
@@ -3080,8 +3078,8 @@ rtwn_temp_calib(struct rtwn_softc *sc)
/* First calibration is performed in rtwn_init(). */
sc->thcal_lctemp = temp;
} else if (abs(temp - sc->thcal_lctemp) > 1) {
- DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n",
- sc->thcal_lctemp, temp));
+ DPRINTF(1, "IQ/LC calib triggered by temp: %d -> %d\n",
+ sc->thcal_lctemp, temp);
rtwn_iq_calib(sc);
rtwn_lc_calib(sc);
/* Record temperature of last calibration. */
rtwn_debug