On Thu, Jul 24, 2025 at 09:05:43AM +1000, Jonathan Gray wrote:
> On Wed, Jul 23, 2025 at 02:12:48PM -0300, Crystal Kolipe wrote:
> > On Wed, Jul 23, 2025 at 10:36:06AM -0600, Theo de Raadt wrote:
> > > Claudio Jeker <cjeker@diehard.n-r-g.com> wrote:
> > > 
> > > > On Wed, Jul 23, 2025 at 08:42:30AM -0600, Theo de Raadt wrote:
> > > > > I think this overstates the importance of this difference over other
> > > > > parts of the cpu description.  I think there's a lot of optimism that
> > > > > this matters for performing work.  Why do we need to print this, if
> > > > > we aren't taking this into account during processing because we have no
> > > > > code to make use of this difference?
> > > > 
> > > > Adding support for this can be only done if we have topology information
> > > > that has more information.
> > > 
> > > The provided diff does not place the information in a data structure so
> > > that the kernel can make a decision.
> > 
> > It also doesn't distinguish between E and LP-E cores.
> > 
> > For that, if I'm not mistaken, you need to check the cache bits of leaf 0x04:
> 
> That assumes knowledge of the cpu model it is running on.
> 
> https://community.intel.com/t5/Mobile-and-Desktop-Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/td-p/1577956
> "Currently, there is no documented or officially sanctioned solution
> that can be deemed future-proof."

That's going to complicate things going forward.

We definitely want to detect LP-E cores, because as far as I can see it
doesn't make much sense to schedule regular workloads on them.  To be honest,
these chips, (at least the ones I've seen), seem to thermal throttle quite
aggresively, making it dubious to even use all of the P cores simultaneously
unless it's for a burstable workload.

So a long compile maxing out all P, E, and LP-E cores is going to perform
badly, quite possibly worse than just using the P cores.

But with this lack of a propper detection method we can't even reliably avoid
the LP-E cores and just not schedule processes on them at all, unless we add
separate logic for each processor generation.