Hi,

SMMUv2's TCR IRGNx/ORGNx/SHx attributes are related to memory associated
with translation table walks.  Since our translation tables are always
WBWA, there's no need to check the coherent flag.  The coherent flag is
only relevant to figure out whether or not we have to flush the caches
for changes to the translation table.

This should be a no-op as I believe that most or all of the machines we
support with an SMMUv2 have a DMA coherent tag.

Please give this a run on machines where "dmesg | grep ^smmu" shows some
output.

Cheers,
Patrick

diff --git a/sys/arch/arm64/dev/smmu.c b/sys/arch/arm64/dev/smmu.c
index 2f81a568069..f57796fdb97 100644
--- a/sys/arch/arm64/dev/smmu.c
+++ b/sys/arch/arm64/dev/smmu.c
@@ -743,7 +743,9 @@ smmu_v2_domain_create(struct smmu_domain *dom)
 	if (iovabits >= 40)
 		dom->sd_4level = 1;
 
-	reg = SMMU_CB_TCR_TG0_4KB | SMMU_CB_TCR_T0SZ(64 - iovabits);
+	reg = SMMU_CB_TCR_TG0_4KB | SMMU_CB_TCR_T0SZ(64 - iovabits) |
+	    SMMU_CB_TCR_IRGN0_WBWA | SMMU_CB_TCR_ORGN0_WBWA |
+	    SMMU_CB_TCR_SH0_ISH;
 	if (dom->sd_stage == 1) {
 		reg |= SMMU_CB_TCR_EPD1;
 	} else {
@@ -772,12 +774,6 @@ smmu_v2_domain_create(struct smmu_domain *dom)
 			break;
 		}
 	}
-	if (sc->sc_coherent)
-		reg |= SMMU_CB_TCR_IRGN0_WBWA | SMMU_CB_TCR_ORGN0_WBWA |
-		    SMMU_CB_TCR_SH0_ISH;
-	else
-		reg |= SMMU_CB_TCR_IRGN0_NC | SMMU_CB_TCR_ORGN0_NC |
-		    SMMU_CB_TCR_SH0_OSH;
 	smmu_cb_write_4(sc, dom->sd_cb_idx, SMMU_CB_TCR, reg);
 
 	if (dom->sd_4level) {