On Thu, Nov 27, 2025 at 03:32:14PM +0100, hshoexer wrote:
> Hi,
>
> as vmd(8) direct kernel launch now uses 32-bit legacy mode (with
> paging disabled) we do not need the 64-bit #VC handling in locore0
> anymore.
>
> ok?
>

ok mlarkin

> Take care,
> HJ.
> --------------------------------------------------------------------
> diff --git a/sys/arch/amd64/amd64/locore0.S b/sys/arch/amd64/amd64/locore0.S
> index 7e971fd999d..b623468f8c9 100644
> --- a/sys/arch/amd64/amd64/locore0.S
> +++ b/sys/arch/amd64/amd64/locore0.S
> @@ -200,16 +200,6 @@ bi_size_ok:
>  	 * Setup temporary #VC trap handler, in case we are running
>  	 * on an AMD CPU in SEV-ES guest mode.  Will be reset by
>  	 * init_x86_64().
> -	 * We are setting up two handlers:
> -	 *
> -	 * 1) locore_vc_trap32:  Triggered when we are running in
> -	 *    32-bit legacy mode.
> -	 *
> -	 * 2) locore_vc_trap64:  Triggered when we are running in
> -	 *    32-bit compatibility mode.
> -	 *
> -	 * The latter one is used by vmd(8) when direct kernel
> -	 * launch is configured.
>  	 */
>  	movl	$RELOC(early_idt), %ecx
>  	movl	$T_VC, %edx
> @@ -229,23 +219,6 @@ bi_size_ok:
>  	orl	$((0x80 | SDT_SYS386IGT) << 8), %eax
>  	movl	%eax, 4(%ecx)
>
> -	movl	$RELOC(early_idt), %ecx
> -	movl	$(2 * T_VC), %edx
> -	leal	(%ecx, %edx, 8), %ecx		/* 64bit #VC IDT slot */
> -
> -	movl	$RELOC(locore_vc_trap64), %eax
> -	andl	$0x0000ffff, %eax
> -	orl	$(GSEL(3, SEL_KPL) << 16), %eax
> -	movl	%eax, (%ecx)
> -
> -	movl	$RELOC(locore_vc_trap64), %eax
> -	andl	$0xffff0000, %eax
> -	orl	$((0x80 | SDT_SYS386IGT) << 8), %eax
> -	movl	%eax, 4(%ecx)
> -	xorl	%eax, %eax
> -	movl	%eax, 8(%ecx)
> -	movl	%eax, 12(%ecx)
> -
>  	movl	$RELOC(idtlc), %eax
>  	lidt	(%eax)
>
> @@ -832,62 +805,6 @@ longmode_hi:
>  	call	init_x86_64
>  	call	main
>
> -vc_cpuid64:
> -	shll	$30, %eax		/* requested register */
> -	orl	$MSR_PROTO_CPUID_REQ, %eax
> -	movl	%ebx, %edx		/* CPUID function */
> -	movl	$MSR_SEV_GHCB, %ecx
> -	wrmsr
> -	rep vmmcall
> -	rdmsr
> -	ret
> -	lfence
> -
> -	.globl	locore_vc_trap64
> -locore_vc_trap64:
> -	pushq	%rax
> -	pushq	%rbx
> -	pushq	%rcx
> -	pushq	%rdx
> -
> -	cmpl	$SVM_VMEXIT_CPUID, 32(%rsp)
> -	jne	.Lterminate64
> -
> -	movl	%eax, %ebx		/* save CPUID function */
> -
> -	movl	$0, %eax		/* request cpuid, get %eax */
> -	call	vc_cpuid64
> -	movq	%rdx, 24(%rsp)
> -
> -	movl	$1, %eax		/* get %ebx */
> -	call	vc_cpuid64
> -	movq	%rdx, 16(%rsp)
> -
> -	movl	$2, %eax		/* get %ecx */
> -	call	vc_cpuid64
> -	movq	%rdx, 8(%rsp)
> -
> -	movl	$3, %eax		/* get %edx */
> -	call	vc_cpuid64
> -	movq	%rdx, 0(%rsp)
> -
> -	popq	%rdx
> -	popq	%rcx
> -	popq	%rbx
> -	popq	%rax
> -	addq	$8, %rsp
> -	addq	$2, (%rsp)
> -	iretq
> -
> -.Lterminate64:
> -	movl	$MSR_PROTO_TERMINATE, %eax
> -	movl	$MSR_SEV_GHCB, %ecx
> -	wrmsr
> -	rep vmmcall
> -.Lterm_loop64:
> -	hlt
> -	jmp	.Lterm_loop64
> -
>  	.code32
>  vc_cpuid32:
>  	shll	$30, %eax		/* requested register */
> @@ -959,7 +876,6 @@ locore_vc_trap32:
>  	hlt
>  	jmp	.Lterm_loop32
>
> -
>  	.section .codepatch,"a"
>  	.align	8, 0xcc
>  	.globl codepatch_begin
>