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compiler_rt: Enable Quad-precision float support for amd64
On Thu Feb 19, 2026 at 10:39:24PM -0500, Brad Smith wrote:
> Enable the Quad-precision float support for amd64
>
> https://github.com/llvm/llvm-project/commit/910a4bf5b70ae14e7262677a8880ee98056e44e1
> https://github.com/llvm/llvm-project/commit/d2ce3e9621411f3391def327f89e3a650918989f
>
>
> This fixes an issue I ran into quite awhile ago with fmt and float128 support.
>
> This was all fixed with compiler-rt as of LLVM 18.
>
> ld: error: undefined symbol: __unordtf2
> >>> referenced by format-test.cc
> >>> test/CMakeFiles/format-test.dir/format-test.cc.o:(fmt::v11::basic_appender<char> fmt::v11::detail::write_float<char, fmt::v11::basic_appender<char>, __float128>(fmt::v11::basic_appender<char>, __float128, fmt::v11::format_specs, fmt::v11::detail::locale_ref))
>
> ld: error: undefined symbol: __netf2
> >>> referenced by format-test.cc
> >>> test/CMakeFiles/format-test.dir/format-test.cc.o:(int fmt::v11::detail::format_float<__float128>(__float128, int, fmt::v11::format_specs const&, bool, fmt::v11::detail::buffer<char>&))
>
> ld: error: undefined symbol: __trunctfsf2
> >>> referenced by format-test.cc
> >>> test/CMakeFiles/format-test.dir/format-test.cc.o:(int fmt::v11::detail::format_float<__float128>(__float128, int, fmt::v11::format_specs const&, bool, fmt::v11::detail::buffer<char>&))
> c++: error: linker command failed with exit code 1 (use -v to see invocation)
> ninja: build stopped: subcommand failed.
>
>
Thanks Brad,
I can confirm that. I think the problem happened because
"GEN_SRCS+=${GEN_TF_SRCS}" was present above and at first glance it did
not appear to be in the if block of aarch64.
Let's put it all in one place so that these problems do not occur again.
Index: Makefile
===================================================================
RCS file: /cvs/src/gnu/lib/libcompiler_rt/Makefile,v
diff -u -p -r1.14 Makefile
--- Makefile 10 Sep 2025 03:38:56 -0000 1.14
+++ Makefile 27 Feb 2026 06:59:07 -0000
@@ -211,9 +211,6 @@ GEN_SRCS+= floatdidf \
.PATH: ${.CURDIR}/../../llvm/compiler-rt/lib/builtins/cpu_model
SRCS+= aarch64.c
-# Quad-precision float support
-GEN_SRCS+= ${GEN_TF_SRCS}
-
# Prepare multiple versions of the LSE-helper
CPPFLAGS+=-DHAS_ASM_LSE
.for pat in cas swp ldadd ldclr ldeor ldset
@@ -305,25 +302,17 @@ SRCS+= divxc3.c \
trunctfxf2.c
.endif
-.if ${RTARCH} == "mips64" || ${RTARCH} == "mips64el"
-# Quad-precision float support
-GEN_SRCS+= ${GEN_TF_SRCS}
-.endif
-
-.if ${RTARCH} == "ppc"
-# Omit "double-double" functions since long double is the same as
-# double on OpenBSD.
-.endif
-
.if ${RTARCH} == "riscv"
-# Quad-precision float support
-GEN_SRCS+= ${GEN_TF_SRCS}
SRCS+= restore.S \
save.S
.endif
-.if ${RTARCH} == "sparc64"
# Quad-precision float support
+# Omit "double-double" functions since long double is the same as
+# double on ppc
+.if ${RTARCH} == "mips64" || ${RTARCH} == "mips64el" \
+ || ${RTARCH} == "sparc64" || ${RTARCH} == "aarch64" \
+ || ${RTARCH} == "x86_64" || ${RTARCH} == "riscv"
GEN_SRCS+= ${GEN_TF_SRCS}
.endif
compiler_rt: Enable Quad-precision float support for amd64