Hi everyone,

Sorry for chiming in, but shouldn’t DIV(7, 2) be written as DIV(6, 2)
for RK3528_CLK_PPLL_100M_MATRIX?

In the Linux definition of CLK_PPLL_100M_MATRIX, the same data is
given as div_shift = 2, div_width = 5. If I'm not mistaken, that
should translate to DIV(6, 2) in OpenBSD. The
RK3528_CLK_MATRIX_50M_SRC clock is already defined that way.

One more question for Jonathan: did you manage to get the Radxa E20C
to survive warm reboots? Every time I reboot the board, U-Boot fails
to bring up PCIe and prints the following message:

pcie_dw_rockchip pcie@fe000000: PCIe-0 Link Fail

It looks like the current OpenBSD code leaves PCIe in a state that
U-Boot cannot properly reinitialize.