On Tue 16 Jun 2026 at 00:42, Mike Larkin <mlarkin@nested.page> wrote:

>
> how do you deliver IPIs without a lapic?


I haven’t emulated fully a LAPIC yet only a few bits. I guess for this PoC
I found out that I don’t need one yet but my approach could be wrong, of
course.

The guest sends IPIs by writing the x2APIC ICR MSR (0x830). That’s a wrmsr,
so it traps as an MSR exit rather than hitting a LAPIC register page. vmm
decodes the delivery mode, destination and vector and forwards a synthetic
exit to vmd, which injects the vector on the target vcpu’s next entry via
the VMX entry-interruption field, similar to how it’s done for i8259 PIC
vectors.

So delivery is hardware event injection, not an APIC, I haven’t
emulated/modelled APIC register file (IRR/ISR/TPR/EOI).

>