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riscv64: enable vector extension before reading vlenb
hi,
similar to the mail about scounteren, the V spec says accessing V csrs
without VS enabled gets an illegal instruction exception.
explicitly set VS to initial value before accessing vlenb to fix it,
which fixes an early panic in cpu_identify.
diff --git a/sys/arch/riscv64/riscv64/cpu.c b/sys/arch/riscv64/riscv64/cpu.c
index a7b0df257f7..6d2bafa9629 100644
--- a/sys/arch/riscv64/riscv64/cpu.c
+++ b/sys/arch/riscv64/riscv64/cpu.c
@@ -279,7 +279,10 @@ cpu_identify(struct cpu_info *ci)
}
if ((riscv_hwcap & HWCAP_ISA_V) != 0) {
+ /* Reading a vector CSR with sstatus.VS off traps. */
+ csr_set(sstatus, SSTATUS_VS_INITIAL);
vlenb = csr_read(vlenb);
+ csr_clear(sstatus, SSTATUS_VS_MASK);
if (CPU_IS_PRIMARY(ci)) {
if (vlenb > VLEN_BYTES_MAX) {
riscv64: enable vector extension before reading vlenb