On Wed, Sep 02, 2026 at 10:42:45AM -0400, Dave Voutila wrote:
> I believe we've talked about this a few times and already agreed to draw
> the line in support for AMD hardware here. This means hardware generally
> from 2011 and newer...at family 12h and newer to have both nested paging
> and NRIP save functionality.
> 
> I really want to make this a hard requirement. vmm's SVM paths make some
> horrible assumptions on instruction length which is a no-no given the
> infinite sadness that is x86/amd64. One can do stupid things like
> REX-prefix a 1-byte instruction like HLT into 15-bytes and it's totally
> legit. We can't just assume "oh, HLT! advance RIP 1 byte!".
> 
> After this lands, I'm going to rip out and replace those assumptions
> with NRIP-based updates.

ok!

> ---
> diff 1f7a70dcb9f781503d2ba25327b18662791e7f3c 634d78817507d651e2cbb7ff8f644036988e94dc
> commit - 1f7a70dcb9f781503d2ba25327b18662791e7f3c
> commit + 634d78817507d651e2cbb7ff8f644036988e94dc
> blob - d84bfe95bad74a5b26013d09dc372941c77634fe
> blob + 5ab1f825910c4a831af042fb519add04ce660d4a
> --- sys/arch/amd64/amd64/identcpu.c
> +++ sys/arch/amd64/amd64/identcpu.c
> @@ -1054,12 +1054,13 @@ cpu_check_vmm_cap(struct cpu_info *ci)
>  	}
> 
>  	/*
> -	 * Check for SVM Nested Paging
> +	 * Check for SVM Nested Paging and NRIP Save.
>  	 */
>  	if ((ci->ci_vmm_flags & CI_VMM_SVM) &&
>  	    ci->ci_pnfeatset >= CPUID_AMD_SVM_CAP) {
>  		CPUID(CPUID_AMD_SVM_CAP, dummy, dummy, dummy, cap);
> -		if (cap & AMD_SVM_NESTED_PAGING_CAP)
> +		if ((cap & AMD_SVM_NESTED_PAGING_CAP) &&
> +		    (cap & AMD_SVM_NRIP_SAVE_CAP))
>  			ci->ci_vmm_flags |= CI_VMM_RVI;
>  	}
> 
> blob - f3bc792f5c26b5746f4a35bb9f33bfc87d64960f
> blob + 45d1727bbe8c78b89ac4f956650af171aaf63f23
> --- sys/arch/amd64/include/specialreg.h
> +++ sys/arch/amd64/include/specialreg.h
> @@ -1458,6 +1458,7 @@
>  #define MSR_AMD_VM_HSAVE_PA		0xc0010117
>  #define CPUID_AMD_SVM_CAP		0x8000000A
>  #define AMD_SVM_NESTED_PAGING_CAP	(1 << 0)
> +#define AMD_SVM_NRIP_SAVE_CAP		(1 << 3)
>  #define AMD_SVM_VMCB_CLEAN_CAP		(1 << 5)
>  #define AMD_SVM_FLUSH_BY_ASID_CAP	(1 << 6)
>  #define AMD_SVM_DECODE_ASSIST_CAP	(1 << 7)