tech@,

I had disabled span work queue interrupts across CPUs at octeon at
octciu.c,v 1.20 because fixing logic of ncpus leads to issues on my ER-4
where I haven't used cnmac0.

I ahd spent a gread deal fo digging why it had happened and I think the
cause is clock.c,v 1.47 where splx() was missed because it
"should not be needed here".

I had replaced put that splx() in the right place and reverted that #if 0

Well, the diff works stable on my ER-4 where I was able to reproduce the bug.

Thoughts? Ok?

Index: arch/octeon/dev/octciu.c
===================================================================
RCS file: /home/cvs/src/sys/arch/octeon/dev/octciu.c,v
diff -u -p -r1.21 octciu.c
--- arch/octeon/dev/octciu.c	16 Apr 2026 15:50:58 -0000	1.21
+++ arch/octeon/dev/octciu.c	22 Oct 2026 11:17:52 -0000
@@ -250,12 +250,10 @@ octciu_intr_establish(int irq, int level
 		panic("%s: illegal irq %d", __func__, irq);
 #endif
 
-#if 0
 #ifdef MULTIPROCESSOR
 	/* Span work queue interrupts across CPUs. */
 	if (IS_WORKQ_IRQ(irq))
 		cpuid = irq % ncpus;
-#endif
 #endif
 
 	flags = (level & IPL_MPSAFE) ? CIH_MPSAFE : 0;
Index: arch/mips64/mips64/clock.c
===================================================================
RCS file: /home/cvs/src/sys/arch/mips64/mips64/clock.c,v
diff -u -p -r1.54 clock.c
--- arch/mips64/mips64/clock.c	24 Oct 2023 13:20:10 -0000	1.54
+++ arch/mips64/mips64/clock.c	22 Oct 2026 11:18:24 -0000
@@ -158,7 +158,7 @@ cp0_int5(uint32_t mask, struct trapframe
 #ifdef MULTIPROCESSOR
 	setsr(sr);
 #endif
-	ci->ci_ipl = s;
+	splx(s);
 	return CR_INT_5;	/* Clock is always on 5 */
 }
 


-- 
wbr, Kirill