From: Dave Voutila <dv@sisu.io>
Subject: Re: add endbr64 instruction to as in amd64 base
To: "Lorenz (xha)" <me@xha.li>
Cc: tech@openbsd.org
Date: Fri, 12 Jan 2024 16:31:38 -0500


"Lorenz (xha)" <me@xha.li> writes:

> hi tech@,
>
> can someone take a look at this and maby commit of OK? i didn't
> include the endbr32 instruction because i think it will not be
> needed on openbsd since running 32-bit binaries on amd64 is not
> supported.
>

While 32-bit binaries aren't supported, endbr32 is a valid instruction
in 64-bit mode that results in a 4-byte NOP (assuming no additional
prefixes):

${
  cc -o junk -x c - << EOF
#include <stdio.h>
int main() {
  __asm volatile ("endbr32");
  printf("ok\n");
  return 0;
}
EOF
  ./junk && objdump -d ./junk | grep endbr32
}

ok
    19ed:       f3 0f 1e fb             endbr32

-dv

>
> Index: gnu/usr.bin/binutils-1.17/include/opcode/i386.h
> ===================================================================
> RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/include/opcode/i386.h,v
> retrieving revision 1.11
> diff -u -p -r1.11 i386.h
> --- gnu/usr.bin/binutils-2.17/include/opcode/i386.h	9 Sep 2018 21:59:43 -0000	1.11
> +++ gnu/usr.bin/binutils-2.17/include/opcode/i386.h	10 Jan 2024 12:15:36 -0000
> @@ -1534,6 +1534,9 @@ static const template i386_optab[] =
>  {"invpcid", 2, 0x660f3882, X, CpuNEW|CpuNo64,
> Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, {
> BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } },
>  {"invpcid", 2, 0x660f3882, X, CpuNEW|Cpu64,
> Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, {
> BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } },
>
> +/* Intel Indirect Branch Tracking extensions */
> +{"endbr64", 0, 0xF30F1E, 0xFA, Cpu64, NoSuf|ImmExt, { 0, 0, 0 } },
> +
>  /* sentinel */
>  {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
>  };