From: Dave Voutila <dv@sisu.io>
Subject: Re: add endbr64 instruction to as in amd64 base
To: Philip Guenther <guenther@gmail.com>
Cc: "Lorenz (xha)" <me@xha.li>, tech@openbsd.org
Date: Sun, 14 Jan 2024 17:10:45 -0500


Philip Guenther <guenther@gmail.com> writes:

> Good enough to support Lorenz's work and clearly fills a gap.  ok guenther@
>
> Dave, if you're not able to commit it, I'll do so.

Feel free if you haven't already.

>
> Philip Guenther
>
> On Sat, Jan 13, 2024 at 1:44 AM Lorenz (xha) <me@xha.li> wrote:
>
>  On Fri, Jan 12, 2024 at 04:31:38PM -0500, Dave Voutila wrote:
>  > "Lorenz (xha)" <me@xha.li> writes:
>  >
>  > > hi tech@,
>  > >
>  > > can someone take a look at this and maby commit of OK? i didn't
>  > > include the endbr32 instruction because i think it will not be
>  > > needed on openbsd since running 32-bit binaries on amd64 is not
>  > > supported.
>  > >
>  >
>  > While 32-bit binaries aren't supported, endbr32 is a valid instruction
>  > in 64-bit mode that results in a 4-byte NOP (assuming no additional
>  > prefixes):
>
>  sure, i can include it, here's a patch with the endbr32 instruction:
>
>  Index: gnu/usr.bin/binutils-2.17/include/opcode/i386.h
>  ===================================================================
>  RCS file: /cvs/src/gnu/usr.bin/binutils-2.17/include/opcode/i386.h,v
>  retrieving revision 1.11
>  diff -u -p -r1.11 i386.h
>  --- gnu/usr.bin/binutils-2.17/include/opcode/i386.h     9 Sep 2018 21:59:43 -0000       1.11
>  +++ gnu/usr.bin/binutils-2.17/include/opcode/i386.h     13 Jan 2024 09:42:56 -0000
>  @@ -1534,6 +1534,10 @@ static const template i386_optab[] =
>   {"invpcid", 2, 0x660f3882, X, CpuNEW|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, {
>  BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } },
>   {"invpcid", 2, 0x660f3882, X, CpuNEW|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, {
>  BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } },
>
>  +/* Intel Indirect Branch Tracking extensions */
>  +{"endbr64", 0, 0xF30F1E, 0xFA, Cpu64, NoSuf|ImmExt, { 0, 0, 0 } },
>  +{"endbr32", 0, 0xF30F1E, 0xFB, CpuNo64, NoSuf|ImmExt, { 0, 0, 0 } },
>  +
>   /* sentinel */
>   {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
>   };