From: j@bitminer.ca
Subject: arm64: patch for midr_el1 access
To: Tech <tech@openbsd.org>
Date: Sun, 25 Feb 2024 19:58:12 -0400



This patch adds MIDR_EL1 as a register available via
sysctl.  Some software like flame/blis wants to know
details of the CPU it is running on.

--J

Index: arm64/arm64/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/arm64/arm64/cpu.c,v
retrieving revision 1.104
diff -u -r1.104 cpu.c
--- arm64/arm64/cpu.c	21 Feb 2024 21:50:17 -0000	1.104
+++ arm64/arm64/cpu.c	25 Feb 2024 22:27:20 -0000
@@ -223,6 +223,7 @@
  uint64_t cpu_id_aa64isar2;
  uint64_t cpu_id_aa64pfr0;
  uint64_t cpu_id_aa64pfr1;
+uint64_t cpu_id_midr;

  #ifdef CRYPTO
  int arm64_has_aes;
@@ -498,6 +499,10 @@
  		printf("\n%s: mismatched ID_AA64ISAR2_EL1",
  		    ci->ci_dev->dv_xname);
  	}
+	if (READ_SPECIALREG(midr_el1) != cpu_id_midr) {
+		printf("\n%s: mismatched MIDR_EL1",
+		    ci->ci_dev->dv_xname);
+	}
  	id = READ_SPECIALREG(id_aa64pfr0_el1);
  	/* Allow CSV2/CVS3 to be different. */
  	id &= ~ID_AA64PFR0_CSV2_MASK;
@@ -766,7 +771,7 @@
  	}

  	/*
-	 * ID_AA64PFR0
+	 * ID_AA64PFR1
  	 */
  	id = READ_SPECIALREG(id_aa64pfr1_el1);

@@ -914,6 +919,7 @@
  		cpu_id_aa64isar2 = READ_SPECIALREG(id_aa64isar2_el1);
  		cpu_id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
  		cpu_id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
+		cpu_id_midr = READ_SPECIALREG(midr_el1);

  		/*
  		 * The CSV2/CSV3 "features" are handled on a
@@ -933,6 +939,16 @@
  		cpu_id_aa64pfr0 &= ~ID_AA64PFR0_EL1_MASK;
  		cpu_id_aa64pfr0 &= ~ID_AA64PFR0_EL2_MASK;
  		cpu_id_aa64pfr0 &= ~ID_AA64PFR0_EL3_MASK;
+
+		/*
+		 *  Show only implementor/part/variant/rev
+		 *
+		 */
+		cpu_id_midr &= (
+			  ID_MIDR_IMPL_MASK
+			| ID_MIDR_PART_MASK
+			| ID_MIDR_VAR_MASK
+			| ID_MIDR_REV_MASK );

  		/*
  		 * Lenovo X13s ships with broken EL2 firmware that
Index: arm64/arm64/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/arm64/arm64/machdep.c,v
retrieving revision 1.86
diff -u -r1.86 machdep.c
--- arm64/arm64/machdep.c	21 Feb 2024 01:45:14 -0000	1.86
+++ arm64/arm64/machdep.c	25 Feb 2024 22:27:20 -0000
@@ -375,6 +375,13 @@
  	case CPU_ID_AA64SMFR0:
  	case CPU_ID_AA64ZFR0:
  		return sysctl_rdquad(oldp, oldlenp, newp, 0);
+	case CPU_ID_MIDR:
+		value = 0;
+		value |= cpu_id_midr & ID_MIDR_IMPL_MASK;
+		value |= cpu_id_midr & ID_MIDR_PART_MASK;
+		value |= cpu_id_midr & ID_MIDR_VAR_MASK;
+		value |= cpu_id_midr & ID_MIDR_REV_MASK;
+		return sysctl_rdquad(oldp, oldlenp, newp, value);
  	default:
  		return (sysctl_bounded_arr(cpuctl_vars, nitems(cpuctl_vars),
  		    name, namelen, oldp, oldlenp, newp, newlen));
Index: arm64/include/armreg.h
===================================================================
RCS file: /cvs/src/sys/arch/arm64/include/armreg.h,v
retrieving revision 1.30
diff -u -r1.30 armreg.h
--- arm64/include/armreg.h	29 Nov 2023 23:32:16 -0000	1.30
+++ arm64/include/armreg.h	25 Feb 2024 22:27:20 -0000
@@ -393,6 +393,17 @@
  #define	 ID_AA64ISAR2_CLRBHB_NONE	(0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
  #define	 ID_AA64ISAR2_CLRBHB_IMPL	(0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT)

+/* ID_MIDR_EL1 */
+#define ID_MIDR_MASK			0x00000000ffffffffULL
+#define ID_MIDR_IMPL_SHIFT		24
+#define ID_MIDR_IMPL_MASK		(0xffULL << ID_MIDR_IMPL_SHIFT)
+#define ID_MIDR_PART_SHIFT		4
+#define ID_MIDR_PART_MASK		(0xfffULL << ID_MIDR_PART_SHIFT)
+#define ID_MIDR_VAR_SHIFT		20
+#define ID_MIDR_VAR_MASK		(0xfULL << ID_MIDR_VAR_SHIFT)
+#define ID_MIDR_REV_SHIFT		0
+#define ID_MIDR_REV_MASK		(0xfULL << ID_MIDR_REV_SHIFT)
+
  /* ID_AA64MMFR0_EL1 */
  #define	ID_AA64MMFR0_MASK		0x00000000ffffffffULL
  #define	ID_AA64MMFR0_PA_RANGE_SHIFT	0
Index: arm64/include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/arm64/include/cpu.h,v
retrieving revision 1.42
diff -u -r1.42 cpu.h
--- arm64/include/cpu.h	24 Jan 2024 19:23:39 -0000	1.42
+++ arm64/include/cpu.h	25 Feb 2024 22:27:20 -0000
@@ -37,7 +37,8 @@
  #define	CPU_ID_AA64SMFR0       10
  #define	CPU_ID_AA64ZFR0	       11
  #define	CPU_LIDACTION          12
-#define	CPU_MAXID	       13	/* number of valid machdep ids */
+#define	CPU_ID_MIDR	       13
+#define	CPU_MAXID	       14	/* number of valid machdep ids */

  #define	CTL_MACHDEP_NAMES { \
  	{ 0, 0 }, \
@@ -53,6 +54,7 @@
  	{ "id_aa64smfr0", CTLTYPE_QUAD }, \
  	{ "id_aa64zfr0", CTLTYPE_QUAD }, \
  	{ "lidaction", CTLTYPE_INT }, \
+	{ "id_midr", CTLTYPE_QUAD }, \
  }

  #ifdef _KERNEL
@@ -65,6 +67,7 @@
  extern uint64_t cpu_id_aa64isar1;
  extern uint64_t cpu_id_aa64pfr0;
  extern uint64_t cpu_id_aa64pfr1;
+extern uint64_t cpu_id_midr;

  #include <machine/intr.h>
  #include <machine/frame.h>