From: j@bitminer.ca
Subject: Re: arm64: patch for midr_el1 access
To: tech@openbsd.org
Date: Tue, 5 Mar 2024 08:54:00 -0800

This is an updated patch against -current as of today.

To reiterate:
This adds a new sysctl.machdep.id_midr which is used by
some software such as the BLIS alternative to BLAS
to determine the aarch64 vendor and part and thus
be able to tailor instructions to the actual hardware.

(BLIS already has extensive amd64 support. This patch
allows BLIS to work on aarch64 more effectively.)



--J


 
Index: cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/arm64/arm64/cpu.c,v
retrieving revision 1.107
diff -u -r1.107 cpu.c
--- cpu.c	1 Mar 2024 15:57:43 -0000	1.107
+++ cpu.c	5 Mar 2024 14:25:00 -0000
@@ -223,6 +223,7 @@
 uint64_t cpu_id_aa64isar2;
 uint64_t cpu_id_aa64pfr0;
 uint64_t cpu_id_aa64pfr1;
+uint64_t cpu_id_midr;
 
 #ifdef CRYPTO
 int arm64_has_aes;
@@ -518,6 +519,10 @@
 		printf("\n%s: mismatched ID_AA64ISAR2_EL1",
 		    ci->ci_dev->dv_xname);
 	}
+	if (READ_SPECIALREG(midr_el1) != cpu_id_midr) {
+		printf("\n%s: mismatched MIDR_EL1",
+		    ci->ci_dev->dv_xname);
+	}
 	id = READ_SPECIALREG(id_aa64pfr0_el1);
 	/* Allow CSV2/CVS3 to be different. */
 	id &= ~ID_AA64PFR0_CSV2_MASK;
@@ -947,6 +952,7 @@
 		cpu_id_aa64isar2 = READ_SPECIALREG(id_aa64isar2_el1);
 		cpu_id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
 		cpu_id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
+		cpu_id_midr = READ_SPECIALREG(midr_el1);
 
 		/*
 		 * The CSV2/CSV3 "features" are handled on a
Index: machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/arm64/arm64/machdep.c,v
retrieving revision 1.86
diff -u -r1.86 machdep.c
--- machdep.c	21 Feb 2024 01:45:14 -0000	1.86
+++ machdep.c	5 Mar 2024 14:25:00 -0000
@@ -375,6 +375,13 @@
 	case CPU_ID_AA64SMFR0:
 	case CPU_ID_AA64ZFR0:
 		return sysctl_rdquad(oldp, oldlenp, newp, 0);
+	case CPU_ID_MIDR:
+		value = 0;
+		value |= cpu_id_midr & ID_MIDR_IMPL_MASK;
+		value |= cpu_id_midr & ID_MIDR_PART_MASK;
+		value |= cpu_id_midr & ID_MIDR_VAR_MASK;
+		value |= cpu_id_midr & ID_MIDR_REV_MASK;
+		return sysctl_rdquad(oldp, oldlenp, newp, value);
 	default:
 		return (sysctl_bounded_arr(cpuctl_vars, nitems(cpuctl_vars),
 		    name, namelen, oldp, oldlenp, newp, newlen));