From: George Koehler Subject: Re: improve spinning in mtx_enter To: Jeremie Courreges-Anglas Cc: Alexander Bluhm , Mark Kettenis , Martin Pieuchot , mjguzik@gmail.com, tech@openbsd.org, gkoehler@openbsd.org Date: Thu, 28 Mar 2024 19:28:59 -0400 On Wed, 27 Mar 2024 19:50:44 +0100 Jeremie Courreges-Anglas wrote: > Shouldn't powerpc64 and other affected archs (mips64, powerpc, maybe > m88k?) switch to: > > #define CPU_BUSY_CYCLE() __asm volatile("" ::: "memory") > > in the MULTIPROCESSOR case? Looks like powerpc64 might also be able > to use the "wait" instruction here but I can't test that (+cc > gkoehler). "wait" is the wrong instruction; the powerpc64 would wait for an interrupt or a hardware event. uses "or 27,27,27" on powerpc and powerpc64, in their cpu_relax function, which is "pause" on Intel and "yield" on Arm. I also see "or 27,27,27" in FreeBSD's cpu_spinwait. "or 27,27,27" is a NOP but might also tell the thread to yield. A comment in boost mentions POWER7. I don't know if "or 27,27,27" affects any cpu that runs OpenBSD. I have a POWER9; the manuals for POWER9 and its Power ISA 3.0B don't mention "or 27,27,27". POWER9 has other instructions like "or 1,1,1" to set low thread priority and "or 2,2,2" to set normal thread priority. OpenBSD disables SMT and runs only a single thread on each core, so changes to thread priority might not be useful. --gkoehler