From: "Theo de Raadt" Subject: Re: print intel hybrid cpu topology information in dmesg To: Janne Johansson Cc: Mark Kettenis , David Gwynne , tech@openbsd.org Date: Sat, 31 Aug 2024 13:09:51 -0600 I don't see the point of two #ifdefs. Janne Johansson wrote: > Den fre 22 dec. 2023 kl 10:22 skrev Mark Kettenis : > > > > > however, we (openbsd) don't make it easy to see the hybrid topology. the > > > > > cpuid info such as vendor, model, brand, family, model, etc is all the > > > > > same between all the cores on these cpus, you have to look at intel > > > > > specific bits to differentiate between the different types of cores. > > > > It is possible to tell by the L1/L2 cache. Yours is easier to spot though. > > > > > this is a first step toward that which puts the info in dmesg. according > > > > > to this link: > > > > as for the choice of names, i don't think there's a right answer > > > yet, ie we don't know if intel will reuse the values when or if > > > they change their microarchitectures underneath p and e cores, or if > > > they'll use different values. most of all i just dont want to have > > > "Core core" in dmesg. > > > > Printing something in dmesg probably makes sense. If we do something > > more than just printing stuff at some point in the future, a bit more > > thought will be needed through as other architectures also have > > machines with cores that have different performance characteristics. > > In the arm64 world there are now SoCs that integrate three different > > core types! > > On the other hand, it seems mips64 and octeons print out info on all > secondary processors that they got from the primary cpu, so it is > literally copying the first processor info to all the secondaries and > then printing that one over and over. > This patch will shrink the dmesg a bit: > > Index: mips64/mips64/cpu.c > =================================================================== > RCS file: /cvs/src/sys/arch/mips64/mips64/cpu.c,v > retrieving revision 1.84 > diff -u -p -u -r1.84 cpu.c > --- mips64/mips64/cpu.c 17 Aug 2024 13:35:01 -0000 1.84 > +++ mips64/mips64/cpu.c 31 Aug 2024 11:39:17 -0000 > @@ -238,6 +238,9 @@ cpuattach(struct device *parent, struct > printf(" rev %d.%d", vers_maj, vers_min); > printf("\n"); > > +#ifdef MULTIPROCESSOR > + if (CPU_IS_PRIMARY(ci)) { > +#endif > if (ci->ci_l1inst.sets == ci->ci_l1data.sets) { > printf("cpu%d: cache L1-I %dKB D %dKB ", cpuno, > ci->ci_l1inst.size / 1024, ci->ci_l1data.size / 1024); > @@ -286,6 +289,9 @@ cpuattach(struct device *parent, struct > } > > printf("\n"); > +#ifdef MULTIPROCESSOR > + } > +#endif > > #ifdef DEBUG > > printf("cpu%d: L1 set size %d:%d\n", cpuno, > > > If the comment at > https://cvsweb.openbsd.org/cgi-bin/cvsweb/src/sys/arch/mips64/mips64/cpu.c.diff?r1=1.52&r2=1.53&f=h > is correct, then it is just parroting the same L1,L2,L3 cache > information over and over for no good reason. > > snippet of dmesg before: > > mainbus0 at root: board 20020 rev 1.15, model cavium,ebb7304 > cpu0 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu0: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu1 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu1: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu2 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu2: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu3 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu3: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu4 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu4: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > ... upto cpu16.. > dmesg after: > > mainbus0 at root: board 20020 rev 1.15, model cavium,ebb7304 > cpu0 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu0: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way > cpu1 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu2 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu3 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu4 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > cpu5 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 > .. and so on. > > / jj@ > > > -- > May the most significant bit of your life be positive. >