From: Marcus Glocker Subject: Re: smmu(4) on QC Laptops To: Patrick Wildt Cc: Mark Kettenis , tech@openbsd.org, tobhe@openbsd.org, mlarkin@openbsd.org Date: Thu, 14 Aug 2025 21:31:28 +0200 On Sat, Aug 02, 2025 at 04:24:01PM +0200, Marcus Glocker wrote: > On Fri, Aug 01, 2025 at 10:21:21PM +0200, Marcus Glocker wrote: > > > On Fri, Aug 01, 2025 at 09:21:37PM +0200, Patrick Wildt wrote: > > > > > On Sat, May 24, 2025 at 07:21:59AM +0200, Patrick Wildt wrote: > > > > On Fri, May 23, 2025 at 07:58:29PM +0200, Mark Kettenis wrote: > > > > > > Date: Fri, 23 May 2025 08:46:16 +0200 > > > > > > From: Patrick Wildt > > > > > > Cc: kettenis@openbsd.org, tobhe@openbsd.org, mlarkin@openbsd.org > > > > > > Content-Type: text/plain; charset=us-ascii > > > > > > Content-Disposition: inline > > > > > > > > > > > > Hi, > > > > > > > > > > > > Nearly three years ago we disabled smmu(4) for QC laptops because they > > > > > > just rebooted instantly. I've finally gone to the bottom of why this > > > > > > happens. > > > > > > > > > > > > On servers we usually boot up with most peripherals not doing any kind > > > > > > of DMA. A serial console is kind of the only thing we depend on, which > > > > > > usually doesn't use DMA for simplicity. Everything else, like NVMe or > > > > > > USB will get turned on later. For those use cases it's been perfectly > > > > > > fine to just turn the SMMU on with strict filtering, because only once > > > > > > the driver configures puts in a job DMA transactions will occur. > > > > > > > > > > > > On the QC laptops the framebuffer goes through an SMMU. That's one of > > > > > > the reasons we need to keep the streams alive and actively put them into > > > > > > a bypass context, which we do! As soon as a driver attaches, we move > > > > > > the stream over into a strict translation context. > > > > > > > > > > > > Unfortunately the changes I did were not completely sufficient. > > > > > > > > > > > > (1) The IOMMU enforcement happens before the driver gets a chance to > > > > > > stop current work. > > > > > > > > > > > > simplebus(4) creates an IOMMU-bound DMA tag before it attempts to attach > > > > > > the children. This leads do two interesting things: > > > > > > > > > > > > (a) If a simplebus(4) has an IOMMU assigned, it is passed an IOMMU-bound > > > > > > DMA tag. All children will get subjected to it. > > > > > > > > > > > > smmu1: establishing sid 0x423 > > > > > > simplebus1 at simplebus0: "geniqup" > > > > > > "serial" at simplebus1 not configured > > > > > > smmu1: establishing sid 0x123 > > > > > > simplebus2 at simplebus0: "geniqup" > > > > > > > > > > > > (b) If there's no driver to be found, the IOMMU-bound DMA tag is created > > > > > > anyway. > > > > > > > > > > > > smmu1: establishing sid 0x1c00 > > > > > > smmu1: took over 8/1c00/2 for sid 1c00 > > > > > > "display-subsystem" at simplebus0 not configured > > > > > > > > > > > > The good thing is that (a) is not a problem in this case as we do not > > > > > > have any active transactions such mappings, as far as I can see on the > > > > > > X1E. But the framebuffer is behind the display-subsystem which is now > > > > > > subjected to strict IOMMU configuration, making us need to fix (b). > > > > > > > > > > > > One idea I have is that we keep all the setup code where it is, at > > > > > > IOMMU-bound DMA tag creation time, but only move the stream to the > > > > > > strict context block once someone(TM) creates a DMA map using this > > > > > > tag. > > > > > > > > > > > > Is that a reasonable thing to do? I don't think anyone would be doing > > > > > > DMA without creating a DMA map first, right? > > > > > > > > > > Correct. > > > > > > > > > > I'm not sure how this is going to work if we want to write a driver > > > > > for the display controller. Presumably we'd create IOMMU mappings for > > > > > the initial framebuffer. But to do so, we'd need to create a DMA map > > > > > first, and when we do that... game over? > > > > > > > > > > So maybe we need to do the takeover when we do the first DMA map load, > > > > > after we've entered the mappings into the page table? But that only > > > > > works if we have a single mapping for the framebuffer. > > > > > > > > I was hoping that we'd have code that first turns off the transactions, > > > > making us "go blind" until we re-enable it with the new address. But > > > > yes, that would require the disable sequence to happen before the map > > > > is created. We could do it on load, which is kind of a hot-path. I > > > > was hoping for now we put it into map create and tackle this once or > > > > if we get around to writing this driver. > > > > > > > > > On the Apple systems, the framebuffer is also behind an IOMMU. There > > > > > we have some code that creates some initial mappings based on > > > > > information from the device tree. > > > > > > > > > > > (2) Re-use of SMRs doesn't take mask in account. > > > > > > > > > > > > In (1b) you can see that the display subsystem is using sid 0x1c00 with > > > > > > mask 0x2, matching to the following SMR: > > > > > > > > > > > > smmu1: SMR[8] = 0x1c00/0x2 > > > > > > > > > > > > We'd like to re-use that if possible, but because of the strict mask > > > > > > checking that wasn't possible. So I'd like to take the mask into > > > > > > consideration when "taking over" streams. This is only done on QC! > > > > > > > > > > Sorry, you'll have to explain to me what what the SMRs do... > > > > > > > > Think work slightly different depending on SMMU version/feature flags, > > > > but for this machine it works an IOMMU setup like this: > > > > > > > > You configure a context block. The context block is basically the IOMMU > > > > group that owns the pagetable. To assign devices to a context block, > > > > you setup a "Stream Mapping Register", e.g.: > > > > > > > > * Allocate + setup context block 3 (e.g. IOMMU group 3) > > > > * This is the actual pagetable and translation setup > > > > * Allocate a stream map entry (can be any, e.g. 5) > > > > * The array has a fixed length, we need to use one slot to > > > > point device to context block. > > > > * Write(SMR(5), DeviceId + Mask + Valid) > > > > * For each DMA transaction, the SMMUs stream mapping function will > > > > iterate the stream map registers to find an enty where: > > > > StreamId & Mask == DeviceId & Mask > > > > * In this example, after writing SMR(5), slot 5 should match > > > > * Write(S2CR(5) = 3) > > > > * This points stream map 5 to context block 3 > > > > * In this example, after the HW's lookup function returns 5, it will > > > > look into S2CR(5) to find which context block it belongs to > > > > > > > > On this laptop, the SMRs basically tell you what devices are currently > > > > enabled to pass through the IOMMU. We update the SMRs to point all > > > > currenetly allowed devices to a "bypass domain", so that existing > > > > traffic goes into a 1:1 translation. > > > > > > > > One we want attach a driver and want to make a device use stricter IOMMU > > > > mappings, we setup a context block and then switch the device from the > > > > bypass IOMMU group/context block to the strict IOMMU group/context > > > > block. > > > > > > > > In reality we're not actually changing the SMR (that's just the filter > > > > rule), we're updating the S2CR to point the stream to a different group. > > > > > > > > But if we don't "take over" the existing SMR mapping, the code will > > > > allocate a new SMR register, and then the IOMMU will complain about a > > > > match conflict because an incoming transaction matches two SMR entries. > > > > > > > > Let me know if I worded this too confusingly! > > > > > > > > > > Please give this a go on machines where `dmesg | grep ^smmu' gives > > > > > > output, and especially on QC machines with X1E, or SC8280XP/ThinkPad > > > > > > x13s. Please send me some dmesgs, as I have added some debug code > > > > > > that I'd like to see run on other machines. :) > > > > > > > > > > Here's the Ampere eMAG machine. ACPI so some of your changes don't > > > > > matter, but it still works with your diff. > > > > > > > > > > > > > Thanks! :) > > > > > > > > Cheers, > > > > Patrick > > > > > > Updated diff that sets the SMR register not just to the stream id but > > > also the mask we kept saved. > > > > Following the fdt dmesgs without, and with your patch, from my > > Samsung Galaxy Book4 Edge. > > I'm not sure what has changed in the meantime, but when I retry your > patch with the latest kernel sources, I'm getting a panic now during > boot triggered by the ufshci(4) DMA allocation: > > https://nazgul.ch/pub/smmu_panic.jpg > > I haven't investigated further yet, just noticed it now. After fixing the ufshci iommus address to 0x1a0 in the samsung dtb, your diff is working. Following: * Your updated smmu diff after your last partial commit to smmu.c -> ok mglocker@ in case you are ok with my ports update :-) * The arm64-qcom-dtb-firmware-2.5 port update including the ufshci iommus address fix. -> ok? * The last dmesg from my samsung. Index: sys/arch/arm64/conf/GENERIC =================================================================== RCS file: /cvs/src/sys/arch/arm64/conf/GENERIC,v diff -u -p -u -p -r1.298 GENERIC --- sys/arch/arm64/conf/GENERIC 9 Aug 2025 14:42:48 -0000 1.298 +++ sys/arch/arm64/conf/GENERIC 14 Aug 2025 18:53:24 -0000 @@ -93,7 +93,7 @@ pci* at pciecam? sdhc* at fdt? sdmmc* at sdhc? bwfm* at sdmmc? # Broadcom FullMAC -smmu* at fdt? +smmu* at fdt? early 1 xhci* at fdt? ccp* at fdt? # AMD Cryptographic Co-processor ipmi* at fdt? Index: sys/arch/arm64/dev/smmu.c =================================================================== RCS file: /cvs/src/sys/arch/arm64/dev/smmu.c,v diff -u -p -u -p -r1.22 smmu.c --- sys/arch/arm64/dev/smmu.c 9 Aug 2025 09:28:03 -0000 1.22 +++ sys/arch/arm64/dev/smmu.c 14 Aug 2025 18:53:25 -0000 @@ -771,6 +771,28 @@ smmu_domain_create(struct smmu_softc *sc reg |= SMMU_CB_SCTLR_ASIDPNE; smmu_cb_write_4(sc, dom->sd_cb_idx, SMMU_CB_SCTLR, reg); + snprintf(dom->sd_exname, sizeof(dom->sd_exname), "%s:%x", + sc->sc_dev.dv_xname, sid); + dom->sd_iovamap = extent_create(dom->sd_exname, 0, + (1LL << iovabits) - 1, M_DEVBUF, NULL, 0, EX_WAITOK | + EX_NOCOALESCE); + + /* Reserve first page (to catch NULL access) */ + extent_alloc_region(dom->sd_iovamap, 0, PAGE_SIZE, EX_WAITOK); + + SIMPLEQ_INSERT_TAIL(&sc->sc_domains, dom, sd_list); + return dom; +} + +static void +smmu_domain_enable(struct smmu_domain *dom) +{ + struct smmu_softc *sc = dom->sd_sc; + uint32_t reg; + + if (dom->sd_enabled) + return; + /* Point stream to context block */ reg = SMMU_S2CR_TYPE_TRANS | dom->sd_cb_idx; if (sc->sc_has_exids && sc->sc_smr) @@ -786,17 +808,7 @@ smmu_domain_create(struct smmu_softc *sc smmu_gr0_write_4(sc, SMMU_SMR(dom->sd_smr_idx), reg); } - snprintf(dom->sd_exname, sizeof(dom->sd_exname), "%s:%x", - sc->sc_dev.dv_xname, sid); - dom->sd_iovamap = extent_create(dom->sd_exname, 0, - (1LL << iovabits) - 1, M_DEVBUF, NULL, 0, EX_WAITOK | - EX_NOCOALESCE); - - /* Reserve first page (to catch NULL access) */ - extent_alloc_region(dom->sd_iovamap, 0, PAGE_SIZE, EX_WAITOK); - - SIMPLEQ_INSERT_TAIL(&sc->sc_domains, dom, sd_list); - return dom; + dom->sd_enabled = 1; } void @@ -1299,6 +1311,8 @@ smmu_dmamap_create(bus_dma_tag_t t, bus_ bus_dmamap_t map; u_long dva, len; int error; + + smmu_domain_enable(dom); error = sc->sc_dmat->_dmamap_create(sc->sc_dmat, size, nsegments, maxsegsz, boundary, flags, &map); Index: sys/arch/arm64/dev/smmu_fdt.c =================================================================== RCS file: /cvs/src/sys/arch/arm64/dev/smmu_fdt.c,v diff -u -p -u -p -r1.7 smmu_fdt.c --- sys/arch/arm64/dev/smmu_fdt.c 2 Jul 2024 19:41:52 -0000 1.7 +++ sys/arch/arm64/dev/smmu_fdt.c 14 Aug 2025 18:53:25 -0000 @@ -89,11 +89,6 @@ smmu_fdt_attach(struct device *parent, s if (OF_getproplen(faa->fa_node, "dma-coherent") == 0) sc->sc_coherent = 1; - if (sc->sc_is_qcom) { - printf(": disabled\n"); - return; - } - if (smmu_attach(sc) != 0) return; Index: sys/arch/arm64/dev/smmuvar.h =================================================================== RCS file: /cvs/src/sys/arch/arm64/dev/smmuvar.h,v diff -u -p -u -p -r1.8 smmuvar.h --- sys/arch/arm64/dev/smmuvar.h 11 Sep 2022 10:18:54 -0000 1.8 +++ sys/arch/arm64/dev/smmuvar.h 14 Aug 2025 18:53:25 -0000 @@ -18,6 +18,7 @@ struct smmu_softc; struct smmu_domain { struct smmu_softc *sd_sc; + uint32_t sd_enabled; uint32_t sd_sid; bus_dma_tag_t sd_dmat; int sd_cb_idx; *** Index: sysutils/firmware/arm64-qcom-dtb/Makefile =================================================================== RCS file: /cvs/ports/sysutils/firmware/arm64-qcom-dtb/Makefile,v diff -u -p -u -p -r1.23 Makefile --- sysutils/firmware/arm64-qcom-dtb/Makefile 10 Jul 2025 11:38:45 -0000 1.23 +++ sysutils/firmware/arm64-qcom-dtb/Makefile 14 Aug 2025 19:13:36 -0000 @@ -1,6 +1,6 @@ FW_DRIVER= arm64-qcom-dtb FW_VER= 2.5 -REVISION= 0 +REVISION= 1 DISTNAME= devicetree-rebasing-6.15-dts Index: sysutils/firmware/arm64-qcom-dtb/patches/patch-src_arm64_qcom_x1e80100_dtsi =================================================================== RCS file: /cvs/ports/sysutils/firmware/arm64-qcom-dtb/patches/patch-src_arm64_qcom_x1e80100_dtsi,v diff -u -p -u -p -r1.5 patch-src_arm64_qcom_x1e80100_dtsi --- sysutils/firmware/arm64-qcom-dtb/patches/patch-src_arm64_qcom_x1e80100_dtsi 8 Jun 2025 18:19:16 -0000 1.5 +++ sysutils/firmware/arm64-qcom-dtb/patches/patch-src_arm64_qcom_x1e80100_dtsi 14 Aug 2025 19:13:36 -0000 @@ -1,6 +1,5 @@ -Index: src/arm64/qcom/x1e80100.dtsi ---- src/arm64/qcom/x1e80100.dtsi.orig -+++ src/arm64/qcom/x1e80100.dtsi +--- src/arm64/qcom/x1e80100.dtsi.orig Thu Aug 14 21:08:50 2025 ++++ src/arm64/qcom/x1e80100.dtsi Thu Aug 14 21:09:14 2025 @@ -71,8 +71,8 @@ reg = <0x0 0x0>; enable-method = "psci"; @@ -173,7 +172,7 @@ Index: src/arm64/qcom/x1e80100.dtsi + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + -+ iommus = <&apps_smmu 0xa0 0x0>; ++ iommus = <&apps_smmu 0x1a0 0x0>; + + clock-names = "core_clk", + "bus_aggr_clk", *** OpenBSD 7.7-current (GENERIC.MP) #0: Thu Aug 14 20:55:49 CEST 2025 hacki@x1e.nazgul.ch:/sys/arch/arm64/compile/GENERIC.MP real mem = 16614113280 (15844MB) avail mem = 16059305984 (15315MB) random: good seed from bootblocks mainbus0 at root: Samsung Galaxy Book4 Edge psci0 at mainbus0: PSCI 1.1, SMCCC 1.3, SYSTEM_SUSPEND efi0 at mainbus0: UEFI 2.7 efi0: American Megatrends rev 0x5001b smbios0 at efi0: SMBIOS 3.3 smbios0: vendor SAMSUNG ELECTRONICS CO., LTD. version "P00AKY.050.250306.WY.1958" date 03/ 6/2025 smbios0: SAMSUNG ELECTRONICS CO., LTD. Galaxy Book4 Edge cpu0 at mainbus0 mpidr 0: Qualcomm Oryon r2p1 cpu0: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu0: 12288KB 64b/line 12-way L2 cache cpu0: RNDR,TLBIOS+IRANGE,TS+AXFLAG,FHM,DP,SM4,SM3,SHA3,RDM,Atomic,CRC32,SHA2+SHA512,SHA1,AES+PMULL,I8MM,BF16,SPECRES,SB,FRINTTS,GPA,LRCPC+LDAPUR,FCMA,JSCVT,APA+EPAC2+FPAC+COMBINED,DPB+DCCVADP,CLRBHB,RPRES,ECV+CNTHCTL,ASID16,AFP,SpecSEI,PAN+ATS1E1+EPAN,LO,HPDS,VH,IDS,AT,CSV3,CSV2,DIT,AMUv1p1,RASv1p1,AdvSIMD+HP,FP+HP,BT,SSBS+MSR cpu1 at mainbus0 mpidr 100: Qualcomm Oryon r2p1 cpu1: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu1: 12288KB 64b/line 12-way L2 cache cpu2 at mainbus0 mpidr 200: Qualcomm Oryon r2p1 cpu2: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu2: 12288KB 64b/line 12-way L2 cache cpu3 at mainbus0 mpidr 300: Qualcomm Oryon r2p1 cpu3: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu3: 12288KB 64b/line 12-way L2 cache cpu4 at mainbus0 mpidr 10000: Qualcomm Oryon r1p1 cpu4: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu4: 12288KB 64b/line 12-way L2 cache cpu5 at mainbus0 mpidr 10100: Qualcomm Oryon r1p1 cpu5: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu5: 12288KB 64b/line 12-way L2 cache cpu6 at mainbus0 mpidr 10200: Qualcomm Oryon r1p1 cpu6: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu6: 12288KB 64b/line 12-way L2 cache cpu7 at mainbus0 mpidr 10300: Qualcomm Oryon r1p1 cpu7: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu7: 12288KB 64b/line 12-way L2 cache cpu8 at mainbus0 mpidr 20000: Qualcomm Oryon r1p1 cpu8: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu8: 12288KB 64b/line 12-way L2 cache cpu9 at mainbus0 mpidr 20100: Qualcomm Oryon r1p1 cpu9: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu9: 12288KB 64b/line 12-way L2 cache cpu10 at mainbus0 mpidr 20200: Qualcomm Oryon r1p1 cpu10: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu10: 12288KB 64b/line 12-way L2 cache cpu11 at mainbus0 mpidr 20300: Qualcomm Oryon r1p1 cpu11: 192KB 64b/line 6-way L1 PIPT I-cache, 96KB 64b/line 6-way L1 D-cache cpu11: 12288KB 64b/line 12-way L2 cache qcscm0 at mainbus0 scmi0 at mainbus0 "gunyah-hyp" at mainbus0 not configured "hyp-elf-package" at mainbus0 not configured "ncc" at mainbus0 not configured "cpucp-log" at mainbus0 not configured "cpucp" at mainbus0 not configured "reserved-region" at mainbus0 not configured "tags-region" at mainbus0 not configured "xbl-dtlog" at mainbus0 not configured "xbl-ramdump" at mainbus0 not configured "aop-image" at mainbus0 not configured "aop-cmd-db" at mainbus0 not configured "aop-config" at mainbus0 not configured "tme-crash-dump" at mainbus0 not configured "tme-log" at mainbus0 not configured "uefi-log" at mainbus0 not configured "secdata-apss" at mainbus0 not configured "pdp-ns-shared" at mainbus0 not configured "gpu-prr" at mainbus0 not configured "tpm-control" at mainbus0 not configured "usb-ucsi-shared" at mainbus0 not configured "pld-pep" at mainbus0 not configured "pld-gmu" at mainbus0 not configured "pld-pdp" at mainbus0 not configured "tz-stat" at mainbus0 not configured "xbl-tmp-buffer" at mainbus0 not configured "adsp-rpc-remote-heap" at mainbus0 not configured "spu-secure-shared-memory" at mainbus0 not configured "adsp-boot-dtb" at mainbus0 not configured "spss-region" at mainbus0 not configured "adsp-boot" at mainbus0 not configured "video" at mainbus0 not configured "adspslpi" at mainbus0 not configured "q6-adsp-dtb" at mainbus0 not configured "cdsp" at mainbus0 not configured "q6-cdsp-dtb" at mainbus0 not configured "gpu-microcode" at mainbus0 not configured "cvp" at mainbus0 not configured "camera" at mainbus0 not configured "av1-encoder" at mainbus0 not configured "reserved-region" at mainbus0 not configured "wpss" at mainbus0 not configured "q6-wpss-dtb" at mainbus0 not configured "xbl-sc" at mainbus0 not configured "reserved-region" at mainbus0 not configured "qtee" at mainbus0 not configured "ta" at mainbus0 not configured "tags" at mainbus0 not configured "llcc-lpi" at mainbus0 not configured qcsmem0 at mainbus0 "linux,cma" at mainbus0 not configured apm0 at mainbus0 "clocks" at mainbus0 not configured "dummy-sink" at mainbus0 not configured "firmware" at mainbus0 not configured "interconnect-0" at mainbus0 not configured "interconnect-1" at mainbus0 not configured "pmu" at mainbus0 not configured "opp-table-qup100mhz" at mainbus0 not configured "opp-table-qup120mhz" at mainbus0 not configured qcsmptp0 at mainbus0 qcsmptp1 at mainbus0 simplebus0 at mainbus0: "soc" qcmtx0 at simplebus0 syscon0 at simplebus0: "clock-controller" smmu0 at simplebus0: 22 CBs (0 S2-only), bypass quirk qcgpio0 at simplebus0 smmu1 at simplebus0: 74 CBs (0 S2-only), bypass quirk agintc0 at simplebus0 shift 4:4 nirq 1024 nredist 12 ipi 0: "interrupt-controller" agintcmsi0 at agintc0 "clock-controller" at simplebus0 not configured qcipcc0 at simplebus0 simplebus1 at simplebus0: "geniqup" "serial" at simplebus1 not configured simplebus2 at simplebus0: "geniqup" qciic0 at simplebus2 iic0 at qciic0 ihidev0 at iic0 addr 0x40 irq, vendor 0x14e5 product 0x650e, hid-over-i2c ihidev0: 10 report ids imt0 at ihidev0: clickpad, 5 contacts wsmouse0 at imt0 mux 0 hid at ihidev0 reportid 5 not configured hid at ihidev0 reportid 6 not configured ims0 at ihidev0 reportid 8: 2 buttons wsmouse1 at ims0 mux 0 hid at ihidev0 reportid 9 not configured hid at ihidev0 reportid 10 not configured simplebus3 at simplebus0: "geniqup" qciic1 at simplebus3 iic1 at qciic1 ihidev1 at iic1 addr 0x5 irq, vendor 0xcf2 product 0x9050, hid-over-i2c ihidev1: 13 report ids ikbd0 at ihidev1 reportid 2: 8 variable keys, 6 key codes wskbd0 at ikbd0: console keyboard icc0 at ihidev1 reportid 4: 1024 usages, 20 keys, array wskbd1 at icc0 mux 1 hid at ihidev1 reportid 7 not configured hid at ihidev1 reportid 8 not configured hid at ihidev1 reportid 13 not configured qctsens0 at simplebus0 qctsens1 at simplebus0 qctsens2 at simplebus0 qctsens3 at simplebus0 "phy" at simplebus0 not configured "phy" at simplebus0 not configured "phy" at simplebus0 not configured "phy" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured dwpcie0 at simplebus0 "phy" at simplebus0 not configured ufshci0 at simplebus0, UFSHCI 4.00 scsibus0 at ufshci0: 2 targets, initiator 0 sd0 at scsibus0 targ 1 lun 0: sd0: 488152MB, 4096 bytes/sector, 124966912 sectors "phy" at simplebus0 not configured "crypto" at simplebus0 not configured "gmu" at simplebus0 not configured "clock-controller" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured qcpas0 at simplebus0 "codec" at simplebus0 not configured "soundwire" at simplebus0 not configured "codec" at simplebus0 not configured "soundwire" at simplebus0 not configured "codec" at simplebus0 not configured "codec" at simplebus0 not configured "soundwire" at simplebus0 not configured "clock-controller" at simplebus0 not configured "soundwire" at simplebus0 not configured "codec" at simplebus0 not configured "pinctrl" at simplebus0 not configured "clock-controller" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured "interconnect" at simplebus0 not configured qcdwusb0 at simplebus0: "usb" xhci0 at qcdwusb0, xHCI 1.10 usb0 at xhci0: USB revision 3.0 uhub0 at usb0 configuration 1 interface 0 "Generic xHCI root hub" rev 3.00/1.00 addr 1 qcdwusb1 at simplebus0: "usb" xhci1 at qcdwusb1, xHCI 1.10 usb1 at xhci1: USB revision 3.0 uhub1 at usb1 configuration 1 interface 0 "Generic xHCI root hub" rev 3.00/1.00 addr 1 qcdrm0 at simplebus0: "display-subsystem" "display-controller" at qcdrm0 not configured qcdpc0 at qcdrm0 "panel" at qcdpc0 not configured "phy" at simplebus0 not configured "clock-controller" at simplebus0 not configured qcpdc0 at simplebus0 qcaoss0 at simplebus0 "sram" at simplebus0 not configured qcspmi0 at simplebus0 qcpmic0 at qcspmi0 sid 0x0 qcpon0 at qcpmic0 qcrtc0 at qcpmic0 qcsdam0 at qcpmic0 qcpmicgpio0 at qcpmic0: no pins qcpwm0 at qcpmic0 qcpmic1 at qcspmi0 sid 0x1 qcpmicgpio1 at qcpmic1: no pins qcpwm1 at qcpmic1 qcpmic2 at qcspmi0 sid 0x2 qcpmicgpio2 at qcpmic2: no pins qcpmic3 at qcspmi0 sid 0x3 qcpmicgpio3 at qcpmic3 qcpmic4 at qcspmi0 sid 0x4 qcpmicgpio4 at qcpmic4 qcpmic5 at qcspmi0 sid 0x5 qcpmicgpio5 at qcpmic5 qcpmic6 at qcspmi0 sid 0x6 qcpmicgpio6 at qcpmic6 qcpmic7 at qcspmi0 sid 0x8 qcpmicgpio7 at qcpmic7: no pins qcpmic8 at qcspmi0 sid 0x9 qcpmicgpio8 at qcpmic8: no pins qcpmic9 at qcspmi0 sid 0xc: transaction dropped qcpmic9: error (5) reading 0x104: unknown PMIC type "stm" at simplebus0 not configured "tpda" at simplebus0 not configured "tpdm" at simplebus0 not configured "funnel" at simplebus0 not configured "funnel" at simplebus0 not configured "funnel" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "funnel" at simplebus0 not configured "cti" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpda" at simplebus0 not configured "funnel" at simplebus0 not configured "funnel" at simplebus0 not configured "tmc" at simplebus0 not configured "replicator" at simplebus0 not configured "tpda" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "funnel" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpda" at simplebus0 not configured "funnel" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpda" at simplebus0 not configured "funnel" at simplebus0 not configured "tpda" at simplebus0 not configured "funnel" at simplebus0 not configured "funnel" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpdm" at simplebus0 not configured "tpda" at simplebus0 not configured "funnel" at simplebus0 not configured qccpucp0 at simplebus0 "rsc" at simplebus0 not configured "timer" at simplebus0 not configured "sram" at simplebus0 not configured "pmu" at simplebus0 not configured "pmu" at simplebus0 not configured "pmu" at simplebus0 not configured "pmu" at simplebus0 not configured "system-cache-controller" at simplebus0 not configured "remoteproc" at simplebus0 not configured pci0 at dwpcie0 ppb0 at pci0 dev 0 function 0 "Qualcomm X1E80100 PCIe" rev 0x00: msi pci1 at ppb0 bus 1 "Qualcomm WCN7850" rev 0x01 at pci1 dev 0 function 0 not configured agtimer0 at mainbus0: 19200 kHz "pmic-glink" at mainbus0 not configured "sound" at mainbus0 not configured "vph-pwr-regulator" at mainbus0 not configured "regulator-edp-3p3" at mainbus0 not configured scmi0: SCMI 2.0 ure0 at uhub1 port 2 configuration 1 interface 0 "TP-LINK USB 10/100/1000 LAN" rev 3.00/30.00 addr 2 ure0: RTL8153 (0x5c20), address 28:ee:52:06:c4:93 rgephy0 at ure0 phy 0: RTL8251, rev. 0 vscsi0 at root scsibus1 at vscsi0: 256 targets softraid0 at root scsibus2 at softraid0: 256 targets root on sd0a (13f744812d2a8646.a) swap on sd0b dump on sd0b qcpas0: failed to shutdown lite firmware scmi0: SCMI_PERF_LEVEL_SET failed qcpas0: failed to receive ready signal qcpas0: failed to boot coprocessor simplefb0 at mainbus0: 2880x1800, 32bpp wsdisplay0 at simplefb0 mux 1: console (std, vt100 emulation), using wskbd0 wskbd1: connecting to wsdisplay0 wsdisplay0: screen 1-5 added (std, vt100 emulation)