From: Hayk Martirosyan <aoglmf@gmail.com>
Subject: Re: rkcomphy: add rk3528 support
To: Jonathan Matthew <jonathan@d14n.org>
Cc: tech@openbsd.org, kettenis@openbsd.org
Date: Thu, 26 Mar 2026 23:39:28 +0400

Hi Jonathan,

On Sun, Mar 22, 2026 at 3:50 PM Jonathan Matthew <jonathan@d14n.org> wrote:
> ...
> With this I can get pcie and the second nic on a Radxa E20C working
> with u-boot 2026.04rc4 and some device tree bits pulled from linux.

Could you please share the changes you applied to u-boot 2026.04-rc4?

I've already tried two approaches.

The first one is based on the next u-boot branch and is described here:
https://marc.info/?l=openbsd-arm&m=177229733717285&w=2
In this case, I get the following error message from u-boot after a warm
reboot:

pcie_dw_rockchip pcie@fe000000: PCIe-0 Link Fail

The second approach is based on the v2026.04-rc4 u-boot tag with
changes in only two files taken from Linux (see below). In this case,
u-boot indeed doesn't touch PCIe, but I get the following error in
dmesg after a warm reboot:

dwpcie0: can't initialize hardware

diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index 12eec2c1db2..b3245275615 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -171,6 +171,10 @@
  };
 };

+&combphy {
+ status = "okay";
+};
+
 &cpu0 {
  cpu-supply = <&vdd_arm>;
 };
@@ -229,6 +233,14 @@
  };
 };

+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pciem1_pins>;
+ reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
 &pinctrl {
  ethernet {
  gmac1_rstn_l: gmac1-rstn-l {
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index d5f8f7b9bf0..d402f282881 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
 #include <dt-bindings/power/rockchip,rk3528-power.h>
@@ -278,10 +279,63 @@

  soc {
  compatible = "simple-bus";
- ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
+ ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>;
  #address-cells = <2>;
  #size-cells = <2>;

+ pcie: pcie@fe000000 {
+ compatible = "rockchip,rk3528-pcie",
+     "rockchip,rk3568-pcie";
+ reg = <0x0 0xfe000000 0x0 0x400000>,
+      <0x0 0xfe4f0000 0x0 0x010000>,
+      <0x0 0xfc000000 0x0 0x100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0xff>;
+ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
+ <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
+ <&cru CLK_PCIE_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+      "aclk_dbi", "pclk",
+      "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
+  "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3528_PD_VPU>;
+ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>,
+ <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
+ resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
  gic: interrupt-controller@fed01000 {
  compatible = "arm,gic-400";
  reg = <0x0 0xfed01000 0 0x1000>,