From: kisekinopureya Subject: Re: [PATCH 0/4] i915 dg2 patches To: Jonathan Gray Cc: tech@openbsd.org Date: Fri, 11 Sep 2026 21:54:43 +0300 I tested your patches as is on latest codebase, it throws uvm_fault and system hard locks: i915_tt_get_st: stub i915_tt_get_st: stub uvm_fault(0xffffffff82b3a700, 0xffffffffffffffda, 0, 1) -> e I tried adding the missing parts from my patches to yours. It boots fine but xenocara and wayland both segfaults. I will investigate it further. About HuC, to my knowledge it handles hardware encode/decode, currently without HuC i can encode h264 and hevc with ffmpeg vaapi. encoding av1 stucks at 0 fps, vp9 throws encoder error. Decoding h264 hevc and vp9 works fine with mpv + vaapi av1 has slight artifacts. here is what i added on top of your diff: diff --git sys/dev/pci/drm/i915/gem/i915_gem_ttm.c sys/dev/pci/drm/i915/gem/i915_gem_ttm.c index 00c4b9768b4..1acaafbdf1e 100644 --- sys/dev/pci/drm/i915/gem/i915_gem_ttm.c +++ sys/dev/pci/drm/i915/gem/i915_gem_ttm.c @@ -296,14 +296,16 @@ err_free_st:  static void i915_ttm_tt_shmem_unpopulate(struct ttm_tt *ttm)  { -    STUB(); -#ifdef notyet      struct i915_ttm_tt *i915_tt = container_of(ttm, typeof(*i915_tt), ttm);      bool backup = ttm->page_flags & TTM_TT_FLAG_SWAPPED;      struct sg_table *st = &i915_tt->cached_rsgt.table; +#ifdef __linux__      shmem_sg_free_table(st, file_inode(i915_tt->filp)->i_mapping,                  backup, backup); +#else +    const size_t size = (size_t)ttm->num_pages << PAGE_SHIFT; +    shmem_sg_free_table(st, NULL, backup, backup, i915_tt->filp, size);  #endif  } @@ -386,13 +388,13 @@ static int i915_ttm_tt_populate(struct ttm_device *bdev,  static void i915_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm)  { -    STUB(); -#ifdef notyet      struct i915_ttm_tt *i915_tt = container_of(ttm, typeof(*i915_tt), ttm);      struct sg_table *st = &i915_tt->cached_rsgt.table; +#ifdef __linux__      if (st->sgl)          dma_unmap_sgtable(i915_tt->dev, st, DMA_BIDIRECTIONAL, 0); +#endif      if (i915_tt->is_shmem) {          i915_ttm_tt_shmem_unpopulate(ttm); @@ -400,7 +402,6 @@ static void i915_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm)          sg_free_table(st);          ttm_pool_free(&bdev->pool, ttm);      } -#endif  }  static void i915_ttm_tt_destroy(struct ttm_device *bdev, struct ttm_tt *ttm) @@ -601,17 +602,19 @@ static void i915_ttm_delete_mem_notify(struct ttm_buffer_object *bo)  static struct i915_refct_sgt *i915_ttm_tt_get_st(struct ttm_tt *ttm)  { -    STUB(); -    return ERR_PTR(-ENOSYS); -#ifdef notyet      struct i915_ttm_tt *i915_tt = container_of(ttm, typeof(*i915_tt), ttm);      struct sg_table *st;      int ret; +    #ifdef __OpenBSD__ +        struct scatterlist *sg; +        unsigned long i; +    #endif      if (i915_tt->cached_rsgt.table.sgl)          return i915_refct_sgt_get(&i915_tt->cached_rsgt);      st = &i915_tt->cached_rsgt.table; +#ifdef __linux__      ret = sg_alloc_table_from_pages_segment(st,              ttm->pages, ttm->num_pages,              0, (unsigned long)ttm->num_pages << PAGE_SHIFT, @@ -620,15 +623,32 @@ static struct i915_refct_sgt *i915_ttm_tt_get_st(struct ttm_tt *ttm)          st->sgl = NULL;          return ERR_PTR(ret);      } +#else +    ret = sg_alloc_table(st, ttm->num_pages, GFP_KERNEL); +    if (ret) { +        st->sgl = NULL; +        return ERR_PTR(ret); +    } +    sg = st->sgl; +    st->nents = 0; +    for (i = 0; i < ttm->num_pages; i++) { +        if (i) +            sg = sg_next(sg); +        st->nents++; +        sg_set_page(sg, ttm->pages[i], PAGE_SIZE, 0); +    } +#endif + +    #ifdef __linux__      ret = dma_map_sgtable(i915_tt->dev, st, DMA_BIDIRECTIONAL, 0);      if (ret) {          sg_free_table(st);          return ERR_PTR(ret);      } +#endif      return i915_refct_sgt_get(&i915_tt->cached_rsgt); -#endif  }  /** diff --git sys/dev/pci/drm/i915/gt/intel_sseu.c sys/dev/pci/drm/i915/gt/intel_sseu.c index 9b53e6a61f4..10d40ee5050 100644 --- sys/dev/pci/drm/i915/gt/intel_sseu.c +++ sys/dev/pci/drm/i915/gt/intel_sseu.c @@ -871,13 +871,10 @@ void intel_sseu_print_ss_info(const char *type,  u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,                        int dss_per_slice)  { -    STUB(); -    return 0; -#ifdef notyet      intel_sseu_ss_mask_t per_slice_mask = {};      unsigned long slice_mask = 0;      int i; - +#ifdef __linux__      WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >          8 * sizeof(slice_mask)); @@ -889,7 +886,35 @@ u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,          bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,                     XEHP_BITMAP_BITS(dss_mask));      } - +#else +    int bit, total_bits; + +    total_bits = XEHP_BITMAP_BITS(dss_mask); + +    WARN_ON(DIV_ROUND_UP(total_bits, dss_per_slice) > 8 * sizeof(slice_mask)); + +    /* Create a mask for checking one slice worth of DSS bits */ +    memset(&per_slice_mask, 0, sizeof(per_slice_mask)); +    for (bit = 0; bit < dss_per_slice && bit < total_bits; bit++) +        per_slice_mask.xehp[bit / 32] |= (1U << (bit % 32)); + +    /* Check each slice's worth of DSS bits */ +    for (i = 0; i < total_bits; i += dss_per_slice) { +        int j, has_dss = 0; + +        /* Check if any DSS bits are set in this slice */ +        for (j = 0; j < dss_per_slice && (i + j) < total_bits; j++) { +            int idx = (i + j) / 32; +            int pos = (i + j) % 32; +            if (dss_mask.xehp[idx] & (1U << pos)) { +                has_dss = 1; +                break; +            } +        } + +        if (has_dss) +            slice_mask |= (1UL << (i / dss_per_slice)); +    }      return slice_mask;  #endif  } diff --git sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c index 21bea4eae3b..b9aafc5395c 100644 --- sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c +++ sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c @@ -110,9 +110,15 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,      fw_def(BROXTON,      0, guc_mmp(bxt,  70, 1, 1)) \      fw_def(SKYLAKE,      0, guc_mmp(skl,  70, 1, 1)) +/* HuC for DG2 is disabled for now + * + * order of definitions matters, it goes below METEORLAKE + * + * fw_def(DG2,          0, huc_gsc(dg2)) + * + */  #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \      fw_def(METEORLAKE,   0, huc_gsc(mtl)) \ -    fw_def(DG2,          0, huc_gsc(dg2)) \      fw_def(ALDERLAKE_P,  0, huc_raw(tgl)) \      fw_def(ALDERLAKE_P,  0, huc_mmp(tgl,  7, 9, 3)) \      fw_def(ALDERLAKE_S,  0, huc_raw(tgl)) \