From: Kevin Lo Subject: rge(4): enable rss/rx queues/tso for rtl8127 To: tech@openbsd.org Date: Thu, 8 Oct 2026 10:28:38 +0800 Hi, This diff adds RX queues/RSS/TSO support and updates microcode for RTL8127. On the RTL8127 the RX and TX descriptors are now the 16-byte format instead of the 32-byte one. TX stays on a single queue. With several tx queues a busy ring starves the higher numbered ones for seconds. Realtek's Linux vendor driver shows the same behaviour, which is presumably why it ships with ENABLE_MULTIPLE_TX_QUEUE disabled. Tested on: rge0 at pci1 dev 0 function 0 "Realtek RTL8127" rev 0x05: msix, 4 rx queues, address 1c:86:0b:xx:xx:xx $ vmstat -iz | grep rge0 irq64/rge0 2 0 irq65/rge0:rx0 432 0 irq66/rge0:rx1 797 1 irq67/rge0:rx2 125 0 irq68/rge0:rx3 130 0 irq69/rge0:tx0 1018 1 Test reports and/or oks welcome. Index: sys/dev/pci/files.pci =================================================================== RCS file: /cvs/src/sys/dev/pci/files.pci,v diff -u -p -u -p -r1.372 files.pci --- sys/dev/pci/files.pci 18 May 2026 12:14:38 -0000 1.372 +++ sys/dev/pci/files.pci 8 Oct 2026 01:53:53 -0000 @@ -860,7 +860,7 @@ attach iavf at pci file dev/pci/if_iavf.c iavf # Realtek 8125 -device rge: ether, ifnet, ifmedia +device rge: ether, ifnet, ifmedia, intrmap, stoeplitz attach rge at pci file dev/pci/if_rge.c rge Index: sys/dev/pci/if_rge.c =================================================================== RCS file: /cvs/src/sys/dev/pci/if_rge.c,v diff -u -p -u -p -r1.45 if_rge.c --- sys/dev/pci/if_rge.c 9 Jul 2026 05:12:34 -0000 1.45 +++ sys/dev/pci/if_rge.c 8 Oct 2026 01:53:53 -0000 @@ -1,7 +1,7 @@ /* $OpenBSD: if_rge.c,v 1.45 2026/07/09 05:12:34 kevlo Exp $ */ /* - * Copyright (c) 2019, 2020, 2023-2025 + * Copyright (c) 2019, 2020, 2023-2026 * Kevin Lo * * Permission to use, copy, modify, and distribute this software for any @@ -28,12 +28,17 @@ #include #include #include +#include #include #include +#include #include #include +#include +#include +#include #if NBPFILTER > 0 #include @@ -65,6 +70,9 @@ int rge_match(struct device *, void *, void rge_attach(struct device *, struct device *, void *); int rge_activate(struct device *, int); int rge_intr(void *); +int rge_intr_link(void *); +int rge_intr_queue(void *); +int rge_intr_tx_queue(void *); int rge_ioctl(struct ifnet *, u_long, caddr_t); void rge_start(struct ifqueue *); void rge_watchdog(struct ifnet *); @@ -72,15 +80,25 @@ void rge_init(struct ifnet *); void rge_stop(struct ifnet *); int rge_ifmedia_upd(struct ifnet *); void rge_ifmedia_sts(struct ifnet *, struct ifmediareq *); -int rge_allocmem(struct rge_softc *); +int rge_rx_dma_alloc(struct rge_softc *, struct rge_queues *); +int rge_tx_dma_alloc(struct rge_softc *, struct rge_queues *); int rge_newbuf(struct rge_queues *); +int rge_rxrinfo(struct rge_softc *, struct if_rxrinfo *); void rge_rx_list_init(struct rge_queues *); void rge_tx_list_init(struct rge_queues *); void rge_fill_rx_ring(struct rge_queues *); +void rge_fill_rx_desc_addr(struct rge_queues *, int); +void rge_fill_tx_desc_addr(struct rge_queues *, int); +void rge_free_rx_ring(struct rge_softc *, struct rge_queues *); +void rge_free_tx_ring(struct rge_softc *, struct rge_queues *); +void rge_rxcsum(struct rge_softc *, uint32_t, uint32_t, + struct mbuf *); +void rge_tx_offload(struct mbuf *, uint32_t *, uint32_t *); int rge_rxeof(struct rge_queues *); int rge_txeof(struct rge_queues *); int rge_reset(struct rge_softc *); void rge_iff(struct rge_softc *); +void rge_init_rss(struct rge_softc *); int rge_chipinit(struct rge_softc *); void rge_set_phy_power(struct rge_softc *, int); void rge_ephy_config(struct rge_softc *); @@ -110,7 +128,10 @@ void rge_add_media_types(struct rge_sof void rge_config_imtype(struct rge_softc *, int); void rge_disable_aspm_clkreq(struct rge_softc *); void rge_disable_hw_im(struct rge_softc *); +void rge_disable_queue(struct rge_softc *, uint32_t); void rge_disable_sim_im(struct rge_softc *); +void rge_enable_queue(struct rge_softc *, uint32_t); +void rge_enable_queues(struct rge_softc *); void rge_setup_sim_im(struct rge_softc *); void rge_setup_intr(struct rge_softc *, int); void rge_switch_mcu_ram_page(struct rge_softc *, int); @@ -127,6 +148,7 @@ void rge_write_phy(struct rge_softc *, uint16_t rge_read_phy(struct rge_softc *, uint16_t, uint16_t); void rge_write_phy_ocp(struct rge_softc *, uint16_t, uint16_t); uint16_t rge_read_phy_ocp(struct rge_softc *, uint16_t); +uint32_t rge_rxstatus_mask(struct rge_softc *, int); int rge_get_link_status(struct rge_softc *); void rge_txstart(void *); void rge_tick(void *); @@ -181,13 +203,13 @@ rge_attach(struct device *parent, struct struct pci_attach_args *pa = aux; pci_chipset_tag_t pc = pa->pa_pc; pci_intr_handle_t ih; - const char *intrstr = NULL; struct ifnet *ifp; - struct rge_queues *q; + int (*isr)(void *); + const char *intrstr = NULL; pcireg_t reg; uint32_t hwrev; uint8_t eaddr[ETHER_ADDR_LEN]; - int offset; + int i, nmsix, offset; pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); @@ -209,39 +231,6 @@ rge_attach(struct device *parent, struct } } - q = malloc(sizeof(struct rge_queues), M_DEVBUF, M_NOWAIT | M_ZERO); - if (q == NULL) { - printf(": unable to allocate queue memory\n"); - return; - } - q->q_sc = sc; - q->q_index = 0; - - sc->sc_queues = q; - sc->sc_nqueues = 1; - - /* - * Allocate interrupt. - */ - if (pci_intr_map_msix(pa, 0, &ih) == 0 || - pci_intr_map_msi(pa, &ih) == 0) - sc->rge_flags |= RGE_FLAG_MSI; - else if (pci_intr_map(pa, &ih) != 0) { - printf(": couldn't map interrupt\n"); - return; - } - intrstr = pci_intr_string(pc, ih); - sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, rge_intr, - sc, sc->sc_dev.dv_xname); - if (sc->sc_ih == NULL) { - printf(": couldn't establish interrupt"); - if (intrstr != NULL) - printf(" at %s", intrstr); - printf("\n"); - return; - } - printf(": %s", intrstr); - sc->sc_dmat = pa->pa_dmat; sc->sc_pc = pa->pa_pc; sc->sc_tag = pa->pa_tag; @@ -271,14 +260,80 @@ rge_attach(struct device *parent, struct printf(": RTL8125D"); break; case 0x6c900000: - sc->rge_type = MAC_R27; + if (rge_read_mac_ocp(sc, 0xd006) == 0x0007) { + sc->rge_type = MAC_R27ATF; + printf(": RTL8127ATF"); + } else + sc->rge_type = MAC_R27; + sc->sc_linkvec = RGE_LINK_VECTOR_8127; + sc->rge_min_msix = RGE_MIN_MSIX_VECTORS_8127; + sc->rge_flags |= RGE_FLAG_DESCV2; break; default: printf(": unknown version 0x%08x\n", hwrev); return; } - rge_config_imtype(sc, RGE_IMTYPE_SIM); + sc->sc_nqueues = sc->sc_ntxqs = 1; + isr = rge_intr; + + if (RGE_TYPE_R27(sc)) { + nmsix = pci_intr_msix_count(pa); + if (nmsix >= sc->rge_min_msix) { + sc->sc_intrmap = intrmap_create(&sc->sc_dev, nmsix, + MIN(RGE_MAX_VECTORS_8127, IF_MAX_VECTORS), + INTRMAP_POWEROF2); + if (sc->sc_intrmap == NULL) { + printf(": unable to create interrupt map\n"); + return; + } + + if (pci_intr_map_msix(pa, sc->sc_linkvec, &ih)) { + printf(": unable to map link vector\n"); + goto intrunmap; + } + + sc->rge_flags |= RGE_FLAG_MULTIVEC; + sc->sc_nqueues = intrmap_count(sc->sc_intrmap); + isr = rge_intr_link; + } + } + + sc->sc_queues = mallocarray(sc->sc_nqueues, sizeof(struct rge_queues), + M_DEVBUF, M_WAITOK | M_ZERO); + if (sc->sc_queues == NULL) { + printf(": unable to create queues\n"); + goto intrunmap; + } + + /* + * Allocate interrupt. + */ + if (!(sc->rge_flags & RGE_FLAG_MULTIVEC)) { + if (pci_intr_map_msix(pa, 0, &ih) == 0 || + pci_intr_map_msi(pa, &ih) == 0) + sc->rge_flags |= RGE_FLAG_MSI; + else if (pci_intr_map(pa, &ih) != 0) { + printf(": couldn't map interrupt\n"); + return; + } + } + + intrstr = pci_intr_string(pc, ih); + sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, isr, sc, + sc->sc_dev.dv_xname); + if (sc->sc_ih == NULL) { + printf(": couldn't establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + goto intrunmap; + } + printf(": %s", intrstr); + + if (sc->sc_nqueues > 1) + printf(", %d rx queue%s", + sc->sc_nqueues, sc->sc_nqueues > 1 ? "s" : ""); /* * PCI Express check. @@ -295,15 +350,19 @@ rge_attach(struct device *parent, struct } if (rge_chipinit(sc)) - return; + goto intrunmap; rge_get_macaddr(sc, eaddr); printf(", address %s\n", ether_sprintf(eaddr)); memcpy(sc->sc_arpcom.ac_enaddr, eaddr, ETHER_ADDR_LEN); - if (rge_allocmem(sc)) - return; + for (i = 0; i < sc->sc_nqueues; i++) { + if (rge_rx_dma_alloc(sc, &sc->sc_queues[i])) + goto intrunmap; + } + if (rge_tx_dma_alloc(sc, &sc->sc_queues[0])) + goto intrunmap; ifp = &sc->sc_arpcom.ac_if; ifp->if_softc = sc; @@ -317,8 +376,11 @@ rge_attach(struct device *parent, struct ifp->if_hardmtu = RGE_JUMBO_MTU; ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | - IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; + IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 | IFCAP_CSUM_TCPv6 | + IFCAP_CSUM_UDPv6; + if (RGE_TYPE_R27(sc)) + ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6; #if NVLAN > 0 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; #endif @@ -329,7 +391,6 @@ rge_attach(struct device *parent, struct rge_wol(ifp, 0); #endif timeout_set(&sc->sc_timeout, rge_tick, sc); - task_set(&sc->sc_task, rge_txstart, sc); /* Initialize ifmedia structures. */ ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd, @@ -342,9 +403,99 @@ rge_attach(struct device *parent, struct if_attach(ifp); ether_ifattach(ifp); + if_attach_iqueues(ifp, sc->sc_nqueues); + for (i = 0; i < sc->sc_nqueues; i++) { + struct ifiqueue *ifiq = ifp->if_iqs[i]; + struct rge_queues *q = &sc->sc_queues[i]; + struct rge_rx *rx = &q->q_rx; + + q->q_sc = sc; + q->q_index = i; + + rx->rge_rx_ifiq = ifiq; + ifiq->ifiq_softc = q; + + if (sc->sc_intrmap) { + if (pci_intr_map_msix(pa, i, &ih)) { + printf("%s: unable to map msi-x vector %d\n", + sc->sc_dev.dv_xname, i); + goto intrdisestablish; + } + snprintf(q->q_name, sizeof(q->q_name), "%s:rx%d", + sc->sc_dev.dv_xname, i); + + q->q_ihc = pci_intr_establish_cpu(sc->sc_pc, ih, + IPL_NET | IPL_MPSAFE, + intrmap_cpu(sc->sc_intrmap, i), + rge_intr_queue, q, q->q_name); + if (q->q_ihc == NULL) { + printf("%s: unable to establish interrupt %d\n", + sc->sc_dev.dv_xname, i); + goto intrdisestablish; + } + } + } + + if_attach_queues(ifp, sc->sc_ntxqs); + for (i = 0; i < sc->sc_ntxqs; i++) { + struct ifqueue *ifq = ifp->if_ifqs[i]; + struct rge_queues *q = &sc->sc_queues[i]; + struct rge_tx *tx = &q->q_tx; + + q->q_tx_index = RGE_TX_VECTOR_8127(i); + task_set(&q->q_task, rge_txstart, q); + tx->rge_tx_ifq = ifq; + ifq->ifq_softc = q; + + if (sc->sc_intrmap) { + if (pci_intr_map_msix(pa, q->q_tx_index, &ih)) { + printf("%s: unable to map msi-x vector %d\n", + sc->sc_dev.dv_xname, i); + goto intrdisestablish; + } + snprintf(q->q_tx_name, sizeof(q->q_tx_name), "%s:tx%d", + sc->sc_dev.dv_xname, i); + + q->q_tx_ihc = pci_intr_establish_cpu(sc->sc_pc, ih, + IPL_NET | IPL_MPSAFE, + intrmap_cpu(sc->sc_intrmap, i), + rge_intr_tx_queue, q, q->q_tx_name); + if (q->q_tx_ihc == NULL) { + printf("%s: unable to establish interrupt %d\n", + sc->sc_dev.dv_xname, i); + goto intrdisestablish; + } + } + } + #if NKSTAT > 0 rge_kstat_attach(sc); #endif + return; + +intrdisestablish: + for (i = 0; i < sc->sc_nqueues; i++) { + struct rge_queues *q = &sc->sc_queues[i]; + + if (q->q_ihc != NULL) { + pci_intr_disestablish(sc->sc_pc, q->q_ihc); + q->q_ihc = NULL; + } + } + for (i = 0; i < sc->sc_ntxqs; i++) { + struct rge_queues *q = &sc->sc_queues[i]; + + if (q->q_tx_ihc != NULL) { + pci_intr_disestablish(sc->sc_pc, q->q_tx_ihc); + q->q_tx_ihc = NULL; + } + } + free(sc->sc_queues, M_DEVBUF, sc->sc_nqueues * sizeof(*sc->sc_queues)); +intrunmap: + if (sc->rge_flags & RGE_FLAG_MULTIVEC) { + intrmap_destroy(sc->sc_intrmap); + sc->sc_intrmap = NULL; + } } int @@ -368,7 +519,7 @@ int rge_intr(void *arg) { struct rge_softc *sc = arg; - struct rge_queues *q = sc->sc_queues; + struct rge_queues *q = &sc->sc_queues[0]; struct ifnet *ifp = &sc->sc_arpcom.ac_if; uint32_t status; int claimed = 0, rv; @@ -435,13 +586,67 @@ rge_intr(void *arg) return (claimed); } +int +rge_intr_link(void *arg) +{ + struct rge_softc *sc = arg; + + rge_disable_queue(sc, sc->sc_linkvec); + rge_link_state(sc); + rge_enable_queue(sc, sc->sc_linkvec); + + return (1); +} + +int +rge_intr_queue(void *arg) +{ + struct rge_queues *q = arg; + struct rge_softc *sc = q->q_sc; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + int claimed = 0; + + rge_disable_queue(sc, q->q_index); + + if (ISSET(ifp->if_flags, IFF_RUNNING)) { + rge_rxeof(q); + claimed = 1; + } + + rge_enable_queue(sc, q->q_index); + + return (claimed); +} + +int +rge_intr_tx_queue(void *arg) +{ + struct rge_queues *q = arg; + struct rge_softc *sc = q->q_sc; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + int claimed = 0; + + rge_disable_queue(sc, q->q_tx_index); + + if (ISSET(ifp->if_flags, IFF_RUNNING)) { + rge_txeof(q); + claimed = 1; + } + + rge_enable_queue(sc, q->q_tx_index); + + return (claimed); +} + static inline void rge_tx_list_sync(struct rge_softc *sc, struct rge_queues *q, unsigned int idx, unsigned int len, int ops) { + int descsz = (sc->rge_flags & RGE_FLAG_DESCV2) ? + sizeof(struct rge_tx_desc_v2) : sizeof(struct rge_tx_desc); + bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, - idx * sizeof(struct rge_tx_desc), len * sizeof(struct rge_tx_desc), - ops); + idx * descsz, len * descsz, ops); } static int @@ -449,9 +654,10 @@ rge_encap(struct ifnet *ifp, struct rge_ { struct rge_softc *sc = q->q_sc; struct rge_tx_desc *d = NULL; + struct rge_tx_desc_v2 *dv2 = NULL; struct rge_txq *txq; bus_dmamap_t txmap; - uint32_t cmdsts, cflags = 0; + uint32_t cmdsts, cflags = 0, tflags = 0; int cur, error, i; #if NBPFILTER > 0 caddr_t if_bpf; @@ -484,31 +690,13 @@ rge_encap(struct ifnet *ifp, struct rge_ bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, BUS_DMASYNC_PREWRITE); - /* - * Set RGE_TDEXTSTS_IPCSUM if any checksum offloading is requested. - * Otherwise, RGE_TDEXTSTS_TCPCSUM / RGE_TDEXTSTS_UDPCSUM does not - * take affect. - */ - if ((m->m_pkthdr.csum_flags & - (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { - cflags |= RGE_TDEXTSTS_IPCSUM; - if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) - cflags |= RGE_TDEXTSTS_TCPCSUM; - if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) - cflags |= RGE_TDEXTSTS_UDPCSUM; - } - - /* Set up hardware VLAN tagging. */ -#if NVLAN > 0 - if (m->m_flags & M_VLANTAG) - cflags |= swap16(m->m_pkthdr.ether_vtag) | RGE_TDEXTSTS_VTAG; -#endif + rge_tx_offload(m, &cflags, &tflags); cur = idx; for (i = 1; i < txmap->dm_nsegs; i++) { cur = RGE_NEXT_TX_DESC(cur); - cmdsts = RGE_TDCMDSTS_OWN; + cmdsts = RGE_TDCMDSTS_OWN | tflags; cmdsts |= txmap->dm_segs[i].ds_len; if (cur == RGE_TX_LIST_CNT - 1) @@ -516,17 +704,24 @@ rge_encap(struct ifnet *ifp, struct rge_ if (i == txmap->dm_nsegs - 1) cmdsts |= RGE_TDCMDSTS_EOF; - d = &q->q_tx.rge_tx_list[cur]; - d->rge_cmdsts = htole32(cmdsts); - d->rge_extsts = htole32(cflags); - d->rge_addr = htole64(txmap->dm_segs[i].ds_addr); + if (sc->rge_flags & RGE_FLAG_DESCV2) { + dv2 = &q->q_tx.rge_tx_list_v2[cur]; + dv2->rge_cmdsts = htole32(cmdsts); + dv2->rge_extsts = htole32(cflags); + dv2->rge_addr = htole64(txmap->dm_segs[i].ds_addr); + } else { + d = &q->q_tx.rge_tx_list[cur]; + d->rge_cmdsts = htole32(cmdsts); + d->rge_extsts = htole32(cflags); + d->rge_addr = htole64(txmap->dm_segs[i].ds_addr); + } } /* Update info of TX queue and descriptors. */ txq->txq_mbuf = m; txq->txq_descidx = cur; - cmdsts = RGE_TDCMDSTS_SOF; + cmdsts = RGE_TDCMDSTS_SOF | tflags; cmdsts |= txmap->dm_segs[0].ds_len; if (idx == RGE_TX_LIST_CNT - 1) @@ -534,10 +729,17 @@ rge_encap(struct ifnet *ifp, struct rge_ if (txmap->dm_nsegs == 1) cmdsts |= RGE_TDCMDSTS_EOF; - d = &q->q_tx.rge_tx_list[idx]; - d->rge_cmdsts = htole32(cmdsts); - d->rge_extsts = htole32(cflags); - d->rge_addr = htole64(txmap->dm_segs[0].ds_addr); + if (sc->rge_flags & RGE_FLAG_DESCV2) { + dv2 = &q->q_tx.rge_tx_list_v2[idx]; + dv2->rge_cmdsts = htole32(cmdsts); + dv2->rge_extsts = htole32(cflags); + dv2->rge_addr = htole64(txmap->dm_segs[0].ds_addr); + } else { + d = &q->q_tx.rge_tx_list[idx]; + d->rge_cmdsts = htole32(cmdsts); + d->rge_extsts = htole32(cflags); + d->rge_addr = htole64(txmap->dm_segs[0].ds_addr); + } if (cur >= idx) { rge_tx_list_sync(sc, q, idx, txmap->dm_nsegs, @@ -552,7 +754,10 @@ rge_encap(struct ifnet *ifp, struct rge_ /* Transfer ownership of packet to the chip. */ cmdsts |= RGE_TDCMDSTS_OWN; rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_POSTWRITE); - d->rge_cmdsts = htole32(cmdsts); + if (sc->rge_flags & RGE_FLAG_DESCV2) + dv2->rge_cmdsts = htole32(cmdsts); + else + d->rge_cmdsts = htole32(cmdsts); rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_PREWRITE); return (txmap->dm_nsegs); @@ -589,8 +794,7 @@ rge_ioctl(struct ifnet *ifp, u_long cmd, error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); break; case SIOCGIFRXR: - error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, - NULL, MCLBYTES, &sc->sc_queues->q_rx.rge_rx_ring); + error = rge_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); break; default: error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); @@ -610,8 +814,7 @@ void rge_start(struct ifqueue *ifq) { struct ifnet *ifp = ifq->ifq_if; - struct rge_softc *sc = ifp->if_softc; - struct rge_queues *q = sc->sc_queues; + struct rge_queues *q = ifq->ifq_softc; struct mbuf *m; int free, idx, used; int queued = 0; @@ -630,7 +833,7 @@ rge_start(struct ifqueue *ifq) for (;;) { if (free < RGE_TX_NSEGS + 2) { - ifq_set_oactive(&ifp->if_snd); + ifq_set_oactive(ifq); break; } @@ -661,7 +864,7 @@ rge_start(struct ifqueue *ifq) ifp->if_timer = 5; q->q_tx.rge_txq_prodidx = idx; - ifq_serialize(ifq, &sc->sc_task); + ifq_serialize(ifq, &q->q_task); } void @@ -679,7 +882,7 @@ void rge_init(struct ifnet *ifp) { struct rge_softc *sc = ifp->if_softc; - struct rge_queues *q = sc->sc_queues; + pcireg_t reg; uint32_t rxconf, val; int i, num_miti; @@ -689,8 +892,9 @@ rge_init(struct ifnet *ifp) rge_set_macaddr(sc, sc->sc_arpcom.ac_enaddr); /* Initialize RX and TX descriptors lists. */ - rge_rx_list_init(q); - rge_tx_list_init(q); + for (i = 0; i < sc->sc_nqueues; i++) + rge_rx_list_init(&sc->sc_queues[i]); + rge_tx_list_init(&sc->sc_queues[0]); if (rge_chipinit(sc)) return; @@ -706,14 +910,9 @@ rge_init(struct ifnet *ifp) RGE_JUMBO_MTU + ETHER_HDR_LEN + 32); /* Load the addresses of the RX and TX lists into the chip. */ - RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO, - RGE_ADDR_LO(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); - RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI, - RGE_ADDR_HI(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); - RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO, - RGE_ADDR_LO(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); - RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI, - RGE_ADDR_HI(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); + for (i = 0; i < sc->sc_nqueues; i++) + rge_fill_rx_desc_addr(&sc->sc_queues[i], i); + rge_fill_tx_desc_addr(&sc->sc_queues[0], 0); /* Set the initial RX and TX configurations. */ if (sc->rge_type == MAC_R25) @@ -724,20 +923,25 @@ rge_init(struct ifnet *ifp) rxconf = RGE_RXCFG_CONFIG_8125D; else rxconf = RGE_RXCFG_CONFIG_8126; + if (sc->rge_flags & RGE_FLAG_DESCV2) + rxconf &= ~RGE_RXCFG_ENBDESCV1; RGE_WRITE_4(sc, RGE_RXCFG, rxconf); RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG); - val = rge_read_csi(sc, 0x70c) & ~0x3f000000; - rge_write_csi(sc, 0x70c, val | 0x27000000); + reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x70c) & ~0x3f000000; + pci_conf_write(sc->sc_pc, sc->sc_tag, 0x70c, reg | 0x27000000); - if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) { + if (RGE_TYPE_R26(sc) || RGE_TYPE_R27(sc)) { /* Disable L1 timeout. */ - val = rge_read_csi(sc, 0x890) & ~0x00000001; - rge_write_csi(sc, 0x890, val); + reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x890) & ~0x00000001; + pci_conf_write(sc->sc_pc, sc->sc_tag, 0x890, reg); } else if (!RGE_TYPE_R25D(sc)) RGE_WRITE_2(sc, 0x0382, 0x221b); - RGE_WRITE_1(sc, RGE_RSS_CTRL, 0); + if (sc->sc_nqueues > 1) + rge_init_rss(sc); + else + RGE_WRITE_4(sc, RGE_RSS_CTRL, 0); val = RGE_READ_2(sc, RGE_RXQUEUE_CTRL) & ~0x001c; RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2); @@ -747,19 +951,25 @@ rge_init(struct ifnet *ifp) rge_write_mac_ocp(sc, 0xc140, 0xffff); rge_write_mac_ocp(sc, 0xc142, 0xffff); - RGE_MAC_SETBIT(sc, 0xeb58, 0x0001); + if (sc->rge_flags & RGE_FLAG_DESCV2) { + val = rge_read_mac_ocp(sc, 0xeb58) & ~0x0003; + rge_write_mac_ocp(sc, 0xeb58, val | 0x0002); + } else + RGE_MAC_SETBIT(sc, 0xeb58, 0x0001); - if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) { - RGE_CLRBIT_1(sc, 0xd8, 0x02); - if (sc->rge_type == MAC_R27) { - RGE_CLRBIT_1(sc, 0x20e4, 0x04); + if (RGE_TYPE_R26(sc) || RGE_TYPE_R27(sc)) { + if (sc->rge_flags & RGE_FLAG_DESCV2) + RGE_SETBIT_1(sc, 0xd8, 0x02); + else + RGE_CLRBIT_1(sc, 0xd8, 0x02); + if (RGE_TYPE_R27(sc)) { RGE_MAC_CLRBIT(sc, 0xe00c, 0x1000); RGE_MAC_CLRBIT(sc, 0xc0c2, 0x0040); } } val = rge_read_mac_ocp(sc, 0xe614); - val &= (sc->rge_type == MAC_R27) ? ~0x0f00 : ~0x0700; + val &= RGE_TYPE_R27(sc) ? ~0x0f00 : ~0x0700; if (sc->rge_type == MAC_R25 || RGE_TYPE_R25D(sc)) rge_write_mac_ocp(sc, 0xe614, val | 0x0300); else if (sc->rge_type == MAC_R25B) @@ -771,7 +981,7 @@ rge_init(struct ifnet *ifp) val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00; rge_write_mac_ocp(sc, 0xe63e, val | - ((fls(sc->sc_nqueues) - 1) & 0x03) << 10); + ((fls(sc->sc_ntxqs) - 1) & 0x03) << 10); val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0030; rge_write_mac_ocp(sc, 0xe63e, val | 0x0020); @@ -808,6 +1018,7 @@ rge_init(struct ifnet *ifp) rge_write_mac_ocp(sc, 0xd430, val | 0x045f); RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN | RGE_DLLPR_TX_10M_PS_EN); + RGE_SETBIT_1(sc, RGE_PPSW, 0x40); if (sc->rge_type == MAC_R25) RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01); @@ -817,7 +1028,7 @@ rge_init(struct ifnet *ifp) RGE_MAC_CLRBIT(sc, 0xe080, 0x0002); } - if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) + if (RGE_TYPE_R26(sc) || RGE_TYPE_R27(sc)) RGE_MAC_CLRBIT(sc, 0xea1c, 0x0304); else RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004); @@ -829,15 +1040,20 @@ rge_init(struct ifnet *ifp) RGE_CLRBIT_2(sc, 0x1880, 0x0030); - if (sc->rge_type == MAC_R27) { + if (RGE_TYPE_R27(sc)) { val = rge_read_mac_ocp(sc, 0xd40c) & ~0xe038; - rge_write_phy_ocp(sc, 0xd40c, val | 0x8020); + rge_write_mac_ocp(sc, 0xd40c, val | 0x8020); } /* Config interrupt type. */ - if (sc->rge_type == MAC_R27) - RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_AVOID_MISS_INTR); - else if (sc->rge_type != MAC_R25) + if (RGE_TYPE_R27(sc)) { + val = RGE_READ_1(sc, RGE_INT_CFG0); + val &= ~(RGE_INT_CFG0_EN | RGE_INT_CFG0_AUTO_CLEAR_IMR | + RGE_INT_CFG0_AVOID_MISS_INTR); + if (sc->rge_flags & RGE_FLAG_MULTIVEC) + val |= RGE_INT_CFG0_EN; + RGE_WRITE_1(sc, RGE_INT_CFG0, val); + } else if (sc->rge_type != MAC_R25) RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_EN); /* Clear timer interrupts. */ @@ -859,6 +1075,15 @@ rge_init(struct ifnet *ifp) RGE_WRITE_2(sc, RGE_INT_CFG1, 0); } + if (sc->rge_flags & RGE_FLAG_MULTIVEC) { + for (i = 0; i < sc->sc_nqueues; i++) { + RGE_WRITE_1(sc, RGE_RX_MULTIVEC_INTMITI(i), + RGE_TIMER_VALUE); + RGE_WRITE_1(sc, RGE_TX_MULTIVEC_INTMITI(i), + RGE_TIMER_VALUE); + } + } + RGE_MAC_SETBIT(sc, 0xc0ac, 0x1f80); rge_write_mac_ocp(sc, 0xe098, 0xc302); @@ -866,6 +1091,7 @@ rge_init(struct ifnet *ifp) RGE_MAC_CLRBIT(sc, 0xe032, 0x0003); val = rge_read_csi(sc, 0x98) & ~0x0000ff00; rge_write_csi(sc, 0x98, val); + DELAY(20); if (RGE_TYPE_R25D(sc)) { val = rge_read_mac_ocp(sc, 0xe092) & ~0x00ff; @@ -880,16 +1106,19 @@ rge_init(struct ifnet *ifp) RGE_READ_2(sc, RGE_CPLUSCMD); /* Set Maximum frame size. */ - RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN); + if (sc->rge_type == MAC_R25 || sc->rge_type == MAC_R25B) + RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN); + else + RGE_WRITE_2(sc, RGE_RXMAXSIZE, + RGE_JUMBO_FRAMELEN | RGE_RXCFG_VLANPHYS); /* Disable RXDV gate. */ RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); - DELAY(2000); /* Program promiscuous mode and multicast filters. */ rge_iff(sc); - if (sc->rge_type == MAC_R27) + if (RGE_TYPE_R27(sc)) RGE_CLRBIT_1(sc, RGE_RADMFIFO_PROTECT, 0x2001); rge_disable_aspm_clkreq(sc); @@ -903,10 +1132,13 @@ rge_init(struct ifnet *ifp) RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB); /* Enable interrupts. */ - rge_setup_intr(sc, RGE_IMTYPE_SIM); + if (sc->rge_flags & RGE_FLAG_MULTIVEC) + rge_enable_queues(sc); + else + rge_setup_intr(sc, RGE_IMTYPE_SIM); ifp->if_flags |= IFF_RUNNING; - ifq_clr_oactive(&ifp->if_snd); + ifq_clr_oactive(ifp->if_ifqs[0]); timeout_add_sec(&sc->sc_timeout, 1); } @@ -918,7 +1150,6 @@ void rge_stop(struct ifnet *ifp) { struct rge_softc *sc = ifp->if_softc; - struct rge_queues *q = sc->sc_queues; int i; timeout_del(&sc->sc_timeout); @@ -936,34 +1167,9 @@ rge_stop(struct ifnet *ifp) RGE_MAC_CLRBIT(sc, 0xc0ac, 0x1f80); intr_barrier(sc->sc_ih); - ifq_barrier(&ifp->if_snd); - ifq_clr_oactive(&ifp->if_snd); - - if (q->q_rx.rge_head != NULL) { - m_freem(q->q_rx.rge_head); - q->q_rx.rge_head = NULL; - q->q_rx.rge_tail = &q->q_rx.rge_head; - } - - /* Free the TX list buffers. */ - for (i = 0; i < RGE_TX_LIST_CNT; i++) { - if (q->q_tx.rge_txq[i].txq_mbuf != NULL) { - bus_dmamap_unload(sc->sc_dmat, - q->q_tx.rge_txq[i].txq_dmamap); - m_freem(q->q_tx.rge_txq[i].txq_mbuf); - q->q_tx.rge_txq[i].txq_mbuf = NULL; - } - } - - /* Free the RX list buffers. */ - for (i = 0; i < RGE_RX_LIST_CNT; i++) { - if (q->q_rx.rge_rxq[i].rxq_mbuf != NULL) { - bus_dmamap_unload(sc->sc_dmat, - q->q_rx.rge_rxq[i].rxq_dmamap); - m_freem(q->q_rx.rge_rxq[i].rxq_mbuf); - q->q_rx.rge_rxq[i].rxq_mbuf = NULL; - } - } + for (i = 0; i < sc->sc_nqueues; i++) + rge_free_rx_ring(sc, &sc->sc_queues[i]); + rge_free_tx_ring(sc, &sc->sc_queues[0]); } /* @@ -981,9 +1187,10 @@ rge_ifmedia_upd(struct ifnet *ifp) /* Disable Gigabit Lite. */ RGE_PHY_CLRBIT(sc, 0xa428, 0x0200); - RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001); - if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) + if (RGE_TYPE_R26(sc) || RGE_TYPE_R27(sc)) RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0007); + else + RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001); val = rge_read_phy_ocp(sc, 0xa5d4); switch (sc->rge_type) { @@ -1092,114 +1299,136 @@ rge_ifmedia_sts(struct ifnet *ifp, struc } } -/* - * Allocate memory for RX/TX rings. - */ int -rge_allocmem(struct rge_softc *sc) +rge_rx_dma_alloc(struct rge_softc *sc, struct rge_queues *q) { - struct rge_queues *q = sc->sc_queues; - int error, i; + void **desc; + int descsz, error, i; - /* Allocate DMA'able memory for the TX ring. */ - error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_SZ, 1, - RGE_TX_LIST_SZ, 0, + if (sc->rge_flags & RGE_FLAG_DESCV2) { + desc = (void **)&q->q_rx.rge_rx_list_v2; + descsz = sizeof(struct rge_rx_desc_v2); + } else { + desc = (void **)&q->q_rx.rge_rx_list; + descsz = sizeof(struct rge_rx_desc); + } + + /* Allocate DMA'able memory for the RX ring. */ + error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_CNT * descsz, 1, + RGE_RX_LIST_CNT * descsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, - &q->q_tx.rge_tx_list_map); + &q->q_rx.rge_rx_list_map); if (error) { - printf("%s: can't create TX list map\n", sc->sc_dev.dv_xname); + printf("%s: can't create RX list map\n", sc->sc_dev.dv_xname); return (error); } - error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0, - &q->q_tx.rge_tx_listseg, 1, &q->q_tx.rge_tx_listnseg, + error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_CNT * descsz, + RGE_ALIGN, 0, &q->q_rx.rge_rx_listseg, 1, &q->q_rx.rge_rx_listnseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_64BIT); if (error) { - printf("%s: can't alloc TX list\n", sc->sc_dev.dv_xname); + printf("%s: can't alloc RX list\n", sc->sc_dev.dv_xname); return (error); } - /* Load the map for the TX ring. */ - error = bus_dmamem_map(sc->sc_dmat, &q->q_tx.rge_tx_listseg, - q->q_tx.rge_tx_listnseg, RGE_TX_LIST_SZ, - (caddr_t *)&q->q_tx.rge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); + /* Load the map for the RX ring. */ + error = bus_dmamem_map(sc->sc_dmat, &q->q_rx.rge_rx_listseg, + q->q_rx.rge_rx_listnseg, RGE_RX_LIST_CNT * descsz, + (caddr_t *)desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); if (error) { - printf("%s: can't map TX dma buffers\n", sc->sc_dev.dv_xname); - bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, - q->q_tx.rge_tx_listnseg); + printf("%s: can't map RX dma buffers\n", sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, + q->q_rx.rge_rx_listnseg); return (error); } - error = bus_dmamap_load(sc->sc_dmat, q->q_tx.rge_tx_list_map, - q->q_tx.rge_tx_list, RGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); + error = bus_dmamap_load(sc->sc_dmat, q->q_rx.rge_rx_list_map, *desc, + RGE_RX_LIST_CNT * descsz, NULL, BUS_DMA_NOWAIT); if (error) { - printf("%s: can't load TX dma map\n", sc->sc_dev.dv_xname); - bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map); - bus_dmamem_unmap(sc->sc_dmat, - (caddr_t)q->q_tx.rge_tx_list, RGE_TX_LIST_SZ); - bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, - q->q_tx.rge_tx_listnseg); + printf("%s: can't load RX dma map\n", sc->sc_dev.dv_xname); + bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map); + bus_dmamem_unmap(sc->sc_dmat, (caddr_t)*desc, + RGE_RX_LIST_CNT * descsz); + bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, + q->q_rx.rge_rx_listnseg); return (error); } - /* Create DMA maps for TX buffers. */ - for (i = 0; i < RGE_TX_LIST_CNT; i++) { - error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, - RGE_TX_NSEGS, RGE_JUMBO_FRAMELEN, 0, + /* Create DMA maps for RX buffers. */ + for (i = 0; i < RGE_RX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1, + RGE_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, - &q->q_tx.rge_txq[i].txq_dmamap); + &q->q_rx.rge_rxq[i].rxq_dmamap); if (error) { - printf("%s: can't create DMA map for TX\n", + printf("%s: can't create DMA map for RX\n", sc->sc_dev.dv_xname); return (error); } } - /* Allocate DMA'able memory for the RX ring. */ - error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_SZ, 1, - RGE_RX_LIST_SZ, 0, + return (error); +} + +int +rge_tx_dma_alloc(struct rge_softc *sc, struct rge_queues *q) +{ + void **desc; + int descsz, error, i; + + if (sc->rge_flags & RGE_FLAG_DESCV2) { + desc = (void **)&q->q_tx.rge_tx_list_v2; + descsz = sizeof(struct rge_tx_desc_v2); + } else { + desc = (void **)&q->q_tx.rge_tx_list; + descsz = sizeof(struct rge_tx_desc); + } + + /* Allocate DMA'able memory for the TX ring. */ + error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_CNT * descsz, 1, + RGE_TX_LIST_CNT * descsz, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, - &q->q_rx.rge_rx_list_map); + &q->q_tx.rge_tx_list_map); if (error) { - printf("%s: can't create RX list map\n", sc->sc_dev.dv_xname); + printf("%s: can't create TX list map\n", sc->sc_dev.dv_xname); return (error); } - error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0, - &q->q_rx.rge_rx_listseg, 1, &q->q_rx.rge_rx_listnseg, + error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_CNT * descsz, + RGE_ALIGN, 0, &q->q_tx.rge_tx_listseg, 1, &q->q_tx.rge_tx_listnseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_64BIT); if (error) { - printf("%s: can't alloc RX list\n", sc->sc_dev.dv_xname); + printf("%s: can't alloc TX list\n", sc->sc_dev.dv_xname); return (error); } - /* Load the map for the RX ring. */ - error = bus_dmamem_map(sc->sc_dmat, &q->q_rx.rge_rx_listseg, - q->q_rx.rge_rx_listnseg, RGE_RX_LIST_SZ, - (caddr_t *)&q->q_rx.rge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); + /* Load the map for the TX ring. */ + error = bus_dmamem_map(sc->sc_dmat, &q->q_tx.rge_tx_listseg, + q->q_tx.rge_tx_listnseg, RGE_TX_LIST_CNT * descsz, + (caddr_t *)desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); if (error) { - printf("%s: can't map RX dma buffers\n", sc->sc_dev.dv_xname); - bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, - q->q_rx.rge_rx_listnseg); + printf("%s: can't map TX dma buffers\n", sc->sc_dev.dv_xname); + bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, + q->q_tx.rge_tx_listnseg); return (error); } - error = bus_dmamap_load(sc->sc_dmat, q->q_rx.rge_rx_list_map, - q->q_rx.rge_rx_list, RGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); + error = bus_dmamap_load(sc->sc_dmat, q->q_tx.rge_tx_list_map, *desc, + RGE_TX_LIST_CNT * descsz, NULL, BUS_DMA_NOWAIT); if (error) { - printf("%s: can't load RX dma map\n", sc->sc_dev.dv_xname); - bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map); - bus_dmamem_unmap(sc->sc_dmat, - (caddr_t)q->q_rx.rge_rx_list, RGE_RX_LIST_SZ); - bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, - q->q_rx.rge_rx_listnseg); + printf("%s: can't load TX dma map\n", sc->sc_dev.dv_xname); + bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map); + bus_dmamem_unmap(sc->sc_dmat, (caddr_t)*desc, + RGE_TX_LIST_CNT * descsz); + bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, + q->q_tx.rge_tx_listnseg); return (error); } - /* Create DMA maps for RX buffers. */ - for (i = 0; i < RGE_RX_LIST_CNT; i++) { - error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1, - RGE_JUMBO_FRAMELEN, 0, + /* Create DMA maps for TX buffers. */ + for (i = 0; i < RGE_TX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat, MAXMCLBYTES, + RGE_TX_NSEGS, RGE_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, - &q->q_rx.rge_rxq[i].rxq_dmamap); + &q->q_tx.rge_txq[i].txq_dmamap); if (error) { - printf("%s: can't create DMA map for RX\n", + printf("%s: can't create DMA map for TX\n", sc->sc_dev.dv_xname); return (error); } @@ -1217,10 +1446,11 @@ rge_newbuf(struct rge_queues *q) struct rge_softc *sc = q->q_sc; struct mbuf *m; struct rge_rx_desc *r; + struct rge_rx_desc_v2 *rv2; struct rge_rxq *rxq; bus_dmamap_t rxmap; uint32_t cmdsts; - int idx; + int descsz, idx; m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES); if (m == NULL) @@ -1241,41 +1471,83 @@ rge_newbuf(struct rge_queues *q) bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); - /* Map the segments into RX descriptors. */ - r = &q->q_rx.rge_rx_list[idx]; - rxq->rxq_mbuf = m; cmdsts = rxmap->dm_segs[0].ds_len; if (idx == RGE_RX_LIST_CNT - 1) cmdsts |= RGE_RDCMDSTS_EOR; - r->hi_qword1.rx_qword4.rge_cmdsts = htole32(cmdsts); - r->hi_qword1.rx_qword4.rge_extsts = htole32(0); - r->hi_qword0.rge_addr = htole64(rxmap->dm_segs[0].ds_addr); - - bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), - BUS_DMASYNC_PREWRITE); + if (sc->rge_flags & RGE_FLAG_DESCV2) { + descsz = sizeof(struct rge_rx_desc_v2); + rv2 = &q->q_rx.rge_rx_list_v2[idx]; + rv2->rx_qword0.rge_cmdsts = htole32(cmdsts); + rv2->rx_qword0.rge_extsts = htole32(0); + rv2->qword0.rge_addr = htole64(rxmap->dm_segs[0].ds_addr); + } else { + descsz = sizeof(struct rge_rx_desc); + r = &q->q_rx.rge_rx_list[idx]; + r->hi_qword1.rx_qword4.rge_cmdsts = htole32(cmdsts); + r->hi_qword1.rx_qword4.rge_extsts = htole32(0); + r->hi_qword0.rge_addr = htole64(rxmap->dm_segs[0].ds_addr); + } + bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, idx * descsz, + descsz, BUS_DMASYNC_PREWRITE); - bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), - BUS_DMASYNC_POSTWRITE); + bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, idx * descsz, + descsz, BUS_DMASYNC_POSTWRITE); cmdsts |= RGE_RDCMDSTS_OWN; - r->hi_qword1.rx_qword4.rge_cmdsts = htole32(cmdsts); - bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + if (sc->rge_flags & RGE_FLAG_DESCV2) + rv2->rx_qword0.rge_cmdsts = htole32(cmdsts); + else + r->hi_qword1.rx_qword4.rge_cmdsts = htole32(cmdsts); + bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, idx * descsz, + descsz, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); q->q_rx.rge_rxq_prodidx = RGE_NEXT_RX_DESC(idx); return (0); } +int +rge_rxrinfo(struct rge_softc *sc, struct if_rxrinfo *ifri) +{ + struct if_rxring_info *ifr; + int i; + int error; + + ifr = mallocarray(sc->sc_nqueues, sizeof(*ifr), M_TEMP, + M_WAITOK | M_ZERO | M_CANFAIL); + if (ifr == NULL) + return (ENOMEM); + + for (i = 0; i < sc->sc_nqueues; i++) { + ifr[i].ifr_size = MCLBYTES; + ifr[i].ifr_info = sc->sc_queues[i].q_rx.rge_rx_ring; + } + + error = if_rxr_info_ioctl(ifri, sc->sc_nqueues, ifr); + free(ifr, M_TEMP, sc->sc_nqueues * sizeof(*ifr)); + + return (error); +} + void rge_rx_list_init(struct rge_queues *q) { - memset(q->q_rx.rge_rx_list, 0, RGE_RX_LIST_SZ); + struct rge_softc *sc = q->q_sc; + void *desc; + int descsz; + + if (sc->rge_flags & RGE_FLAG_DESCV2) { + desc = q->q_rx.rge_rx_list_v2; + descsz = sizeof(struct rge_rx_desc_v2); + } else { + desc = q->q_rx.rge_rx_list; + descsz = sizeof(struct rge_rx_desc); + } + + memset(desc, 0, RGE_RX_LIST_CNT * descsz); q->q_rx.rge_rxq_prodidx = q->q_rx.rge_rxq_considx = 0; q->q_rx.rge_head = NULL; @@ -1299,19 +1571,70 @@ rge_fill_rx_ring(struct rge_queues *q) } void +rge_fill_rx_desc_addr(struct rge_queues *q, int queue) +{ + struct rge_softc *sc = q->q_sc; + + if (queue == 0) { + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO, + RGE_ADDR_LO(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI, + RGE_ADDR_HI(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); + } else { + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO_V2(queue), + RGE_ADDR_LO(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI_V2(queue), + RGE_ADDR_HI(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); + } +} + +void +rge_fill_tx_desc_addr(struct rge_queues *q, int queue) +{ + struct rge_softc *sc = q->q_sc; + + if (queue == 0) { + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO, + RGE_ADDR_LO(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI, + RGE_ADDR_HI(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); + } else { + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO_V2(queue), + RGE_ADDR_LO(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI_V2(queue), + RGE_ADDR_HI(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); + } +} + +void rge_tx_list_init(struct rge_queues *q) { struct rge_softc *sc = q->q_sc; struct rge_tx_desc *d; - int i; + struct rge_tx_desc_v2 *dv2; + void *desc; + int descsz, i; + + if (sc->rge_flags & RGE_FLAG_DESCV2) { + desc = q->q_tx.rge_tx_list_v2; + descsz = sizeof(struct rge_tx_desc_v2); + } else { + desc = q->q_tx.rge_tx_list; + descsz = sizeof(struct rge_tx_desc); + } - memset(q->q_tx.rge_tx_list, 0, RGE_TX_LIST_SZ); + memset(desc, 0, RGE_TX_LIST_CNT * descsz); for (i = 0; i < RGE_TX_LIST_CNT; i++) q->q_tx.rge_txq[i].txq_mbuf = NULL; - d = &q->q_tx.rge_tx_list[RGE_TX_LIST_CNT - 1]; - d->rge_cmdsts = htole32(RGE_TDCMDSTS_EOR); + if (sc->rge_flags & RGE_FLAG_DESCV2) { + dv2 = &q->q_tx.rge_tx_list_v2[RGE_TX_LIST_CNT - 1]; + dv2->rge_cmdsts = htole32(RGE_TDCMDSTS_EOR); + } else { + d = &q->q_tx.rge_tx_list[RGE_TX_LIST_CNT - 1]; + d->rge_cmdsts = htole32(RGE_TDCMDSTS_EOR); + } bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 0, q->q_tx.rge_tx_list_map->dm_mapsize, @@ -1320,6 +1643,135 @@ rge_tx_list_init(struct rge_queues *q) q->q_tx.rge_txq_prodidx = q->q_tx.rge_txq_considx = 0; } +void +rge_free_rx_ring(struct rge_softc *sc, struct rge_queues *q) +{ + int i; + + if (sc->sc_intrmap) + intr_barrier(q->q_ihc); + + if (q->q_rx.rge_head != NULL) { + m_freem(q->q_rx.rge_head); + q->q_rx.rge_head = NULL; + q->q_rx.rge_tail = &q->q_rx.rge_head; + } + + /* Free the RX list buffers. */ + for (i = 0; i < RGE_RX_LIST_CNT; i++) { + if (q->q_rx.rge_rxq[i].rxq_mbuf != NULL) { + bus_dmamap_unload(sc->sc_dmat, + q->q_rx.rge_rxq[i].rxq_dmamap); + m_freem(q->q_rx.rge_rxq[i].rxq_mbuf); + q->q_rx.rge_rxq[i].rxq_mbuf = NULL; + } + } +} + +void +rge_free_tx_ring(struct rge_softc *sc, struct rge_queues *q) +{ + int i; + + ifq_barrier(q->q_tx.rge_tx_ifq); + ifq_clr_oactive(q->q_tx.rge_tx_ifq); + + if (sc->sc_intrmap) + intr_barrier(q->q_tx_ihc); + + /* Free the TX list buffers. */ + for (i = 0; i < RGE_TX_LIST_CNT; i++) { + if (q->q_tx.rge_txq[i].txq_mbuf != NULL) { + bus_dmamap_unload(sc->sc_dmat, + q->q_tx.rge_txq[i].txq_dmamap); + m_freem(q->q_tx.rge_txq[i].txq_mbuf); + q->q_tx.rge_txq[i].txq_mbuf = NULL; + } + } +} + +void +rge_rxcsum(struct rge_softc *sc, uint32_t cmdsts, uint32_t extsts, + struct mbuf *m) +{ + if (sc->rge_flags & RGE_FLAG_DESCV2) { + /* Check IP header checksum. */ + if (!(cmdsts & RGE_RDCMDSTS_IPCSUMERR_V2) && + (extsts & RGE_RDEXTSTS_IPV4)) + m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; + + /* Check TCP/UDP checksum. */ + if ((extsts & (RGE_RDEXTSTS_IPV4 | RGE_RDEXTSTS_IPV6)) && + (((cmdsts & RGE_RDCMDSTS_TCPPKT_V2) && + !(cmdsts & RGE_RDCMDSTS_TCPCSUMERR_V2)) || + ((cmdsts & RGE_RDCMDSTS_UDPPKT_V2) && + !(cmdsts & RGE_RDCMDSTS_UDPCSUMERR_V2)))) + m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | + M_UDP_CSUM_IN_OK; + } else { + /* Check IP header checksum. */ + if (!(extsts & RGE_RDEXTSTS_IPCSUMERR) && + (extsts & RGE_RDEXTSTS_IPV4)) + m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; + + /* Check TCP/UDP checksum. */ + if ((extsts & (RGE_RDEXTSTS_IPV4 | RGE_RDEXTSTS_IPV6)) && + (((extsts & RGE_RDEXTSTS_TCPPKT) && + !(extsts & RGE_RDEXTSTS_TCPCSUMERR)) || + ((extsts & RGE_RDEXTSTS_UDPPKT) && + !(extsts & RGE_RDEXTSTS_UDPCSUMERR)))) + m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | + M_UDP_CSUM_IN_OK; + } +} + +void +rge_tx_offload(struct mbuf *m, uint32_t *cflags, uint32_t *tflags) +{ + struct ether_extracted ext; + uint32_t hdrlen; + + /* Set up hardware VLAN tagging. */ +#if NVLAN > 0 + if (m->m_flags & M_VLANTAG) + *cflags |= swap16(m->m_pkthdr.ether_vtag) | RGE_TDEXTSTS_VTAG; +#endif + + ether_extract_headers(m, &ext); + hdrlen = sizeof(*ext.eh) + ext.iphlen; + + if (m->m_pkthdr.csum_flags & M_TCP_TSO) { + uint32_t outlen; + + if (ext.tcp && m->m_pkthdr.ph_mss > 0 && + hdrlen <= RGE_TDCMDSTS_TCPHO_MAX) { + *tflags = hdrlen << RGE_TDCMDSTS_TCPHO_SHIFT; + outlen = MIN(m->m_pkthdr.ph_mss, RGE_TDEXTSTS_MAX_MSS); + *cflags |= outlen << RGE_TDEXTSTS_MSS_SHIFT; + *cflags |= RGE_TDEXTSTS_TSOENB_V2 | + RGE_TDEXTSTS_TSOTCP_V2; + *cflags |= (ext.ip4) ? + RGE_TDEXTSTS_TSOIPV4_V2 : RGE_TDEXTSTS_TSOIPV6_V2; + + tcpstat_add(tcps_outpkttso, + (ext.paylen + outlen - 1) / outlen); + } else + tcpstat_inc(tcps_outbadtso); + } else if (m->m_pkthdr.csum_flags & + (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) { + if (ext.ip4) + *cflags |= RGE_TDEXTSTS_IPCSUM; +#ifdef INET6 + else if (ext.ip6) + *tflags = hdrlen << RGE_TDCMDSTS_TCPHO_SHIFT; +#endif + if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) + *cflags |= RGE_TDEXTSTS_TCPCSUM; + if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) + *cflags |= RGE_TDEXTSTS_UDPCSUM; + } +} + int rge_rxeof(struct rge_queues *q) { @@ -1329,24 +1781,37 @@ rge_rxeof(struct rge_queues *q) struct ifnet *ifp = &sc->sc_arpcom.ac_if; struct if_rxring *rxr = &q->q_rx.rge_rx_ring; struct rge_rx_desc *cur_rx; + struct rge_rx_desc_v2 *cur_rx_v2; struct rge_rxq *rxq; - uint32_t rxstat, extsts; - int i, mlen, rx = 0; - int cons; + uint32_t extsts, rxstat; + uint32_t hash = 0, hashtype = 0; + int cons, descsz, i, mlen, rx = 0; i = cons = q->q_rx.rge_rxq_considx; - while (if_rxr_inuse(rxr) > 0) { - cur_rx = &q->q_rx.rge_rx_list[i]; + descsz = (sc->rge_flags & RGE_FLAG_DESCV2) ? + sizeof(*cur_rx_v2) : sizeof(*cur_rx); + while (if_rxr_inuse(rxr) > 0) { bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - i * sizeof(*cur_rx), sizeof(*cur_rx), - BUS_DMASYNC_POSTREAD); - rxstat = letoh32(cur_rx->hi_qword1.rx_qword4.rge_cmdsts); + i * descsz, descsz, BUS_DMASYNC_POSTREAD); + + if (sc->rge_flags & RGE_FLAG_DESCV2) { + cur_rx_v2 = &q->q_rx.rge_rx_list_v2[i]; + rxstat = letoh32(cur_rx_v2->rx_qword0.rge_cmdsts); + hash = letoh32(cur_rx_v2->qword0.rx_rss.rge_rss); + hashtype = + letoh32(cur_rx_v2->qword0.rx_rss.rge_hdr_info) & + RGE_RDHDRINFO_RSSTYPE_MASK; + } else { + cur_rx = &q->q_rx.rge_rx_list[i]; + rxstat = + letoh32(cur_rx->hi_qword1.rx_qword4.rge_cmdsts); + } + if (rxstat & RGE_RDCMDSTS_OWN) { bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - i * sizeof(*cur_rx), sizeof(*cur_rx), - BUS_DMASYNC_PREREAD); + i * descsz, descsz, BUS_DMASYNC_PREREAD); break; } @@ -1361,7 +1826,7 @@ rge_rxeof(struct rge_queues *q) if_rxr_put(rxr, 1); rx = 1; - if (ISSET(rxstat, RGE_RDCMDSTS_SOF)) { + if (ISSET(rxstat, rge_rxstatus_mask(sc, CMDSTS_SOF))) { if (q->q_rx.rge_head != NULL) { ifp->if_ierrors++; m_freem(q->q_rx.rge_head); @@ -1384,7 +1849,7 @@ rge_rxeof(struct rge_queues *q) m = q->q_rx.rge_head; m->m_pkthdr.len += mlen; - if (rxstat & RGE_RDCMDSTS_RXERRSUM) { + if (rxstat & rge_rxstatus_mask(sc, CMDSTS_RXERRSUM)) { ifp->if_ierrors++; m_freem(m); q->q_rx.rge_head = NULL; @@ -1392,7 +1857,7 @@ rge_rxeof(struct rge_queues *q) continue; } - if (!ISSET(rxstat, RGE_RDCMDSTS_EOF)) + if (!ISSET(rxstat, rge_rxstatus_mask(sc, CMDSTS_EOF))) continue; q->q_rx.rge_head = NULL; @@ -1400,21 +1865,16 @@ rge_rxeof(struct rge_queues *q) m_adj(m, -ETHER_CRC_LEN); - extsts = letoh32(cur_rx->hi_qword1.rx_qword4.rge_extsts); - - /* Check IP header checksum. */ - if (!(extsts & RGE_RDEXTSTS_IPCSUMERR) && - (extsts & RGE_RDEXTSTS_IPV4)) - m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; - - /* Check TCP/UDP checksum. */ - if ((extsts & (RGE_RDEXTSTS_IPV4 | RGE_RDEXTSTS_IPV6)) && - (((extsts & RGE_RDEXTSTS_TCPPKT) && - !(extsts & RGE_RDEXTSTS_TCPCSUMERR)) || - ((extsts & RGE_RDEXTSTS_UDPPKT) && - !(extsts & RGE_RDEXTSTS_UDPCSUMERR)))) - m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | - M_UDP_CSUM_IN_OK; + extsts = (sc->rge_flags & RGE_FLAG_DESCV2) ? + letoh32(cur_rx_v2->rx_qword0.rge_extsts) : + letoh32(cur_rx->hi_qword1.rx_qword4.rge_extsts); + + rge_rxcsum(sc, rxstat, extsts, m); + + if (hashtype != RGE_RDHDRINFO_RSSTYPE_NONE) { + m->m_pkthdr.ph_flowid = hash; + m->m_pkthdr.csum_flags |= M_FLOWID; + } #if NVLAN > 0 if (extsts & RGE_RDEXTSTS_VTAG) { @@ -1432,21 +1892,18 @@ rge_rxeof(struct rge_queues *q) if (i >= cons) { bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - cons * sizeof(*cur_rx), (i - cons) * sizeof(*cur_rx), - BUS_DMASYNC_POSTWRITE); + cons * descsz, (i - cons) * descsz, BUS_DMASYNC_POSTWRITE); } else { bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - cons * sizeof(*cur_rx), - (RGE_RX_LIST_CNT - cons) * sizeof(*cur_rx), + cons * descsz, (RGE_RX_LIST_CNT - cons) * descsz, BUS_DMASYNC_POSTWRITE); if (i > 0) { bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, - 0, i * sizeof(*cur_rx), - BUS_DMASYNC_POSTWRITE); + 0, i * descsz, BUS_DMASYNC_POSTWRITE); } } - if (ifiq_input(&ifp->if_rcv, &ml)) + if (ifiq_input(q->q_rx.rge_rx_ifiq, &ml)) if_rxr_livelocked(rxr); q->q_rx.rge_rxq_considx = i; @@ -1474,7 +1931,9 @@ rge_txeof(struct rge_queues *q) cur = txq->txq_descidx; rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_POSTREAD); - txstat = q->q_tx.rge_tx_list[cur].rge_cmdsts; + txstat = (sc->rge_flags & RGE_FLAG_DESCV2) ? + q->q_tx.rge_tx_list_v2[cur].rge_cmdsts : + q->q_tx.rge_tx_list[cur].rge_cmdsts; rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_PREREAD); if (ISSET(txstat, htole32(RGE_TDCMDSTS_OWN))) { free = 2; @@ -1512,10 +1971,10 @@ rge_txeof(struct rge_queues *q) q->q_tx.rge_txq_considx = idx; - if (ifq_is_oactive(&ifp->if_snd)) - ifq_restart(&ifp->if_snd); + if (ifq_is_oactive(q->q_tx.rge_tx_ifq)) + ifq_restart(q->q_tx.rge_tx_ifq); else if (free == 2) - ifq_serialize(&ifp->if_snd, &sc->sc_task); + ifq_serialize(q->q_tx.rge_tx_ifq, &q->q_task); else ifp->if_timer = 0; @@ -1622,6 +2081,43 @@ rge_iff(struct rge_softc *sc) RGE_WRITE_4(sc, RGE_MAR4, swap32(hashes[0])); } +void +rge_init_rss(struct rge_softc *sc) +{ + uint32_t rss_key[RGE_RSS_KEY_SIZE / sizeof(uint32_t)]; + uint32_t ctrl, reta = 0; + int i, qid; + + stoeplitz_to_key(rss_key, sizeof(rss_key)); + + ctrl = (fls(sc->sc_nqueues) - 1) << 16; + ctrl |= (RGE_RSS_CTRL_IPV4 | RGE_RSS_CTRL_IPV6); + ctrl |= (RGE_RSS_CTRL_TCP_IPV4 | RGE_RSS_CTRL_TCP_IPV6); + ctrl |= (RGE_RSS_CTRL_IPV6_EXT | RGE_RSS_CTRL_TCP_IPV6_EXT); + ctrl |= (fls(RGE_RSS_MAX_INDTBL_SIZE) - 1) << 8; + RGE_WRITE_4(sc, RGE_RSS_CTRL, ctrl); + + /* Set up the redirection table. */ + for (i = 0; i < RGE_RSS_MAX_INDTBL_SIZE; i++) { + qid = (i % sc->sc_nqueues); + + /* + * The low 8 bits are for hash value (n+0); + * The next 8 bits are for hash value (n+1), etc. + */ + reta = reta >> 8; + reta |= (((uint32_t)qid) << 24); + if ((i & 3) == 3) { + RGE_WRITE_4(sc, RGE_RSS_INDTBL(i >> 2), reta); + reta = 0; + } + } + + /* Now fill our hash function seeds. */ + for (i = 0; i < nitems(rss_key); i++) + RGE_WRITE_4(sc, RGE_RSS_KEY(i), letoh32(rss_key[i])); +} + int rge_chipinit(struct rge_softc *sc) { @@ -1831,7 +2327,7 @@ rge_mac_config_ext_mcu(struct rge_softc rge_write_mac_ocp(sc, 0xfc32, 0x4298); rge_write_mac_ocp(sc, 0xfc3a, 0x234a); rge_write_mac_ocp(sc, 0xfc48, 0x023c); - } else if (type == MAC_R27) { + } else { bps = &rtl8127_mac_bps; mcodever = rge_mcu_get_bin_version(rtl8127_mac_bps_vals, bps->count); @@ -1843,6 +2339,11 @@ rge_mac_config_ext_mcu(struct rge_softc bps->vals[i]); /* Switch to page 1. */ rge_switch_mcu_ram_page(sc, 1); + for (; i < 512; i++) + rge_write_mac_ocp(sc, bps->regs[i], + bps->vals[i]); + /* Switch to page 2. */ + rge_switch_mcu_ram_page(sc, 2); for (; i < bps->count; i++) rge_write_mac_ocp(sc, bps->regs[i], bps->vals[i]); @@ -1856,7 +2357,8 @@ rge_mac_config_ext_mcu(struct rge_softc rge_write_mac_ocp(sc, 0xfc32, 0x0166); rge_write_mac_ocp(sc, 0xfc34, 0x1a6a); rge_write_mac_ocp(sc, 0xfc36, 0x1a2c); - rge_write_mac_ocp(sc, 0xfc48, 0x00ff); + rge_write_mac_ocp(sc, 0xfc3c, 0x1598); + rge_write_mac_ocp(sc, 0xfc48, 0x04ff); } /* Write microcode version. */ @@ -1905,6 +2407,7 @@ rge_ephy_config(struct rge_softc *sc) rge_ephy_config_mac_r25b(sc); break; case MAC_R27: + case MAC_R27ATF: rge_ephy_config_mac_r27(sc); break; default: @@ -1976,6 +2479,7 @@ rge_phy_config(struct rge_softc *sc) ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX)); switch (sc->rge_type) { case MAC_R27: + case MAC_R27ATF: val |= RGE_ADV_10000TFDX; /* fallthrough */ case MAC_R26_1: @@ -2023,6 +2527,7 @@ rge_phy_config(struct rge_softc *sc) rge_phy_config_mac_r26_2(sc); break; case MAC_R27: + case MAC_R27ATF: rge_phy_config_mac_r27(sc); break; default: @@ -2031,6 +2536,8 @@ rge_phy_config(struct rge_softc *sc) RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000); + /* kevlo FIBER PHY */ + /* Disable EEE. */ RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); if (sc->rge_type == MAC_R25) { @@ -2039,10 +2546,11 @@ rge_phy_config(struct rge_softc *sc) } else if (sc->rge_type == MAC_R25B || RGE_TYPE_R25D(sc)) RGE_PHY_SETBIT(sc, 0xa432, 0x0010); - RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006); - RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); - if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) - RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002); + RGE_PHY_CLRBIT(sc, 0xa5d0, RGE_TYPE_R27(sc) ? 0x000e : 0x0006); + if (RGE_TYPE_R26(sc) || RGE_TYPE_R27(sc)) + RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0003); + else + RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200); @@ -2117,16 +2625,16 @@ rge_phy_config_mac_r27(struct rge_softc RGE_PHY_SETBIT(sc, 0xa438, 0x2000); rge_write_phy_ocp(sc, 0xa436, 0x8187); RGE_PHY_SETBIT(sc, 0xa438, 0x2000); - rge_write_phy_ocp(sc, 0xA436, 0x8192); - RGE_PHY_SETBIT(sc, 0xA438, 0x2000); - rge_write_phy_ocp(sc, 0xA436, 0x819D); - RGE_PHY_SETBIT(sc, 0xA438, 0x2000); - rge_write_phy_ocp(sc, 0xA436, 0x81A8); - RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); - rge_write_phy_ocp(sc, 0xA436, 0x81B3); - RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); - rge_write_phy_ocp(sc, 0xA436, 0x81BE); - RGE_PHY_SETBIT(sc, 0xA438, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x8192); + RGE_PHY_SETBIT(sc, 0xa438, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x819d); + RGE_PHY_SETBIT(sc, 0xa438, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x81a8); + RGE_PHY_CLRBIT(sc, 0xa438, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x81b3); + RGE_PHY_CLRBIT(sc, 0xa438, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x81be); + RGE_PHY_SETBIT(sc, 0xa438, 0x2000); rge_write_phy_ocp(sc, 0xa436, 0x817d); val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; rge_write_phy_ocp(sc, 0xa438, val | 0xa600); @@ -2200,6 +2708,18 @@ rge_phy_config_mac_r27(struct rge_softc rge_write_phy_ocp(sc, 0xb87c, 0x82ce); val = rge_read_phy_ocp(sc, 0xb87e) & ~0xf000; rge_write_phy_ocp(sc, 0xb87e, val | 0x4000); + rge_write_phy_ocp(sc, 0xb87c, 0x83a5); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); + rge_write_phy_ocp(sc, 0xb87c, 0x83a6); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); + rge_write_phy_ocp(sc, 0xb87c, 0x83a7); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); + rge_write_phy_ocp(sc, 0xb87c, 0x83a8); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); rge_write_phy_ocp(sc, 0xb87c, 0x84ac); rge_write_phy_ocp(sc, 0xb87e, 0x0000); rge_write_phy_ocp(sc, 0xb87c, 0x84ae); @@ -2212,7 +2732,7 @@ rge_phy_config_mac_r27(struct rge_softc rge_write_phy_ocp(sc, 0xb87c, 0x8ffc); rge_write_phy_ocp(sc, 0xb87e, 0x6008); rge_write_phy_ocp(sc, 0xb87c, 0x8ffe); - rge_write_phy_ocp(sc, 0xb87e, 0xf450); + rge_write_phy_ocp(sc, 0xb87e, 0xf4ff); rge_write_phy_ocp(sc, 0xb87c, 0x8015); RGE_PHY_SETBIT(sc, 0xb87e, 0x0200); rge_write_phy_ocp(sc, 0xb87c, 0x8016); @@ -2323,6 +2843,8 @@ rge_phy_config_mac_r27(struct rge_softc val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; rge_write_phy_ocp(sc, 0xa438, val | 0x1600); RGE_PHY_SETBIT(sc, 0xa430, 0x0003); + RGE_PHY_SETBIT(sc, 0xa442, 0x0080); + RGE_PHY_CLRBIT(sc, 0xa430, 0x1000); } void @@ -3196,8 +3718,8 @@ rge_phy_config_mcu(struct rge_softc *sc, for (i = 0; i < nitems(mac_r26_2_mcu); i++) rge_write_phy_ocp(sc, mac_r26_2_mcu[i].reg, mac_r26_2_mcu[i].val); - } else if (sc->rge_type == MAC_R27) { - for (i = 0; i < 1887; i++) + } else if (RGE_TYPE_R27(sc)) { + for (i = 0; i < 4097; i++) rge_write_phy_ocp(sc, mac_r27_mcu[i].reg, mac_r27_mcu[i].val); rge_patch_phy_mcu(sc, 0); @@ -3260,7 +3782,7 @@ rge_hw_init(struct rge_softc *sc) DELAY(3000); rge_write_mac_ocp(sc, 0xfc26, 0); - if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) + if (RGE_TYPE_R26(sc) || RGE_TYPE_R27(sc)) rge_mac_config_ext_mcu(sc, sc->rge_type); else rge_mac_config_mcu(sc, sc->rge_type); @@ -3278,8 +3800,15 @@ void rge_hw_reset(struct rge_softc *sc) { /* Disable interrupts */ - RGE_WRITE_4(sc, RGE_IMR, 0); - RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR)); + if (sc->rge_flags & RGE_FLAG_MULTIVEC) { + RGE_WRITE_4(sc, RGE_IMR_CLR_V2, 0xffffffff); + RGE_WRITE_4(sc, RGE_IMR_V4, 0xffffffff); + RGE_WRITE_4(sc, RGE_ISR_V2, 0xffffffff); + RGE_WRITE_4(sc, RGE_ISR_V4, 0xffffffff); + } else { + RGE_WRITE_4(sc, RGE_IMR, 0); + RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR)); + } /* Clear timer interrupts. */ RGE_WRITE_4(sc, RGE_TIMERINT0, 0); @@ -3376,7 +3905,7 @@ rge_disable_aspm_clkreq(struct rge_softc if (unlock) RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); - if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) + if (RGE_TYPE_R26(sc) || RGE_TYPE_R27(sc)) RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08); else RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); @@ -3393,6 +3922,15 @@ rge_disable_hw_im(struct rge_softc *sc) } void +rge_disable_queue(struct rge_softc *sc, uint32_t vector) +{ + uint32_t mask = 1 << vector; + + RGE_WRITE_4(sc, RGE_IMR_CLR_V2, mask); + RGE_WRITE_4(sc, RGE_ISR_V2, mask); +} + +void rge_disable_sim_im(struct rge_softc *sc) { RGE_WRITE_4(sc, RGE_TIMERINT0, 0); @@ -3400,6 +3938,28 @@ rge_disable_sim_im(struct rge_softc *sc) } void +rge_enable_queue(struct rge_softc *sc, uint32_t vector) +{ + uint32_t mask = 1 << vector; + + RGE_WRITE_4(sc, RGE_IMR_SET_V2, mask); +} + +void +rge_enable_queues(struct rge_softc *sc) +{ + struct rge_queues *q; + int i; + + for (i = 0, q = sc->sc_queues; i < sc->sc_nqueues; i++, q++) { + rge_enable_queue(sc, q->q_index); + if (i < sc->sc_ntxqs) + rge_enable_queue(sc, q->q_tx_index); + } + rge_enable_queue(sc, sc->sc_linkvec); +} + +void rge_setup_sim_im(struct rge_softc *sc) { RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600); @@ -3668,6 +4228,22 @@ rge_read_phy_ocp(struct rge_softc *sc, u return (val & RGE_PHYOCP_DATA_MASK); } +uint32_t +rge_rxstatus_mask(struct rge_softc *sc, int status) +{ + switch (status) { + case CMDSTS_EOF: + return (sc->rge_flags & RGE_FLAG_DESCV2) ? + RGE_RDCMDSTS_EOF_V2 : RGE_RDCMDSTS_EOF; + case CMDSTS_SOF: + return (sc->rge_flags & RGE_FLAG_DESCV2) ? + RGE_RDCMDSTS_SOF_V2 : RGE_RDCMDSTS_SOF; + default: + return (sc->rge_flags & RGE_FLAG_DESCV2) ? + RGE_RDCMDSTS_RXERRSUM_V2 : RGE_RDCMDSTS_RXERRSUM; + } +} + int rge_get_link_status(struct rge_softc *sc) { @@ -3677,7 +4253,8 @@ rge_get_link_status(struct rge_softc *sc void rge_txstart(void *arg) { - struct rge_softc *sc = arg; + struct rge_queues *q = arg; + struct rge_softc *sc = q->q_sc; RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START); } @@ -3748,7 +4325,6 @@ rge_wol_power(struct rge_softc *sc) { /* Disable RXDV gate. */ RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); - DELAY(2000); RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN); RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN); Index: sys/dev/pci/if_rgereg.h =================================================================== RCS file: /cvs/src/sys/dev/pci/if_rgereg.h,v diff -u -p -u -p -r1.17 if_rgereg.h --- sys/dev/pci/if_rgereg.h 26 Jan 2026 01:45:18 -0000 1.17 +++ sys/dev/pci/if_rgereg.h 8 Oct 2026 01:53:53 -0000 @@ -1,7 +1,8 @@ /* $OpenBSD: if_rgereg.h,v 1.17 2026/01/26 01:45:18 kevlo Exp $ */ /* - * Copyright (c) 2019, 2020, 2025 Kevin Lo + * Copyright (c) 2019, 2020, 2025, 2026 + * Kevin Lo * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -20,64 +21,78 @@ #define RGE_PCI_BAR1 (PCI_MAPREG_START + 4) #define RGE_PCI_BAR2 (PCI_MAPREG_START + 8) -#define RGE_MAC0 0x0000 -#define RGE_MAC4 0x0004 -#define RGE_MAR0 0x0008 -#define RGE_MAR4 0x000c -#define RGE_TXDESC_ADDR_LO 0x0020 -#define RGE_TXDESC_ADDR_HI 0x0024 -#define RGE_INT_CFG0 0x0034 -#define RGE_CMD 0x0037 -#define RGE_IMR 0x0038 -#define RGE_ISR 0x003c -#define RGE_TXCFG 0x0040 -#define RGE_RXCFG 0x0044 -#define RGE_TIMERCNT 0x0048 -#define RGE_EECMD 0x0050 -#define RGE_CFG0 0x0051 -#define RGE_CFG1 0x0052 -#define RGE_CFG2 0x0053 -#define RGE_CFG3 0x0054 -#define RGE_CFG4 0x0055 -#define RGE_CFG5 0x0056 -#define RGE_TDFNR 0x0057 -#define RGE_TIMERINT0 0x0058 -#define RGE_TIMERINT1 0x005c -#define RGE_CSIDR 0x0064 -#define RGE_CSIAR 0x0068 -#define RGE_PHYSTAT 0x006c -#define RGE_PMCH 0x006f -#define RGE_INT_CFG1 0x007a -#define RGE_EPHYAR 0x0080 -#define RGE_TIMERINT2 0x008c -#define RGE_TXSTART 0x0090 -#define RGE_MACOCP 0x00b0 -#define RGE_PHYOCP 0x00b8 -#define RGE_DLLPR 0x00d0 -#define RGE_TWICMD 0x00d2 -#define RGE_MCUCMD 0x00d3 -#define RGE_RXMAXSIZE 0x00da -#define RGE_CPLUSCMD 0x00e0 -#define RGE_IM 0x00e2 -#define RGE_RXDESC_ADDR_LO 0x00e4 -#define RGE_RXDESC_ADDR_HI 0x00e8 -#define RGE_PPSW 0x00f2 -#define RGE_TIMERINT3 0x00f4 -#define RGE_RADMFIFO_PROTECT 0x0402 -#define RGE_INTMITI(i) (0x0a00 + (i) * 4) -#define RGE_PHYBASE 0x0a40 -#define RGE_EPHYAR_EXT_ADDR 0x0ffe -#define RGE_ADDR0 0x19e0 -#define RGE_ADDR1 0x19e4 -#define RGE_RSS_CTRL 0x4500 -#define RGE_RXQUEUE_CTRL 0x4800 -#define RGE_EEE_TXIDLE_TIMER 0x6048 +#define RGE_MAC0 0x0000 +#define RGE_MAC4 0x0004 +#define RGE_MAR0 0x0008 +#define RGE_MAR4 0x000c +#define RGE_TXDESC_ADDR_LO 0x0020 +#define RGE_TXDESC_ADDR_HI 0x0024 +#define RGE_INT_CFG0 0x0034 +#define RGE_CMD 0x0037 +#define RGE_IMR 0x0038 +#define RGE_ISR 0x003c +#define RGE_TXCFG 0x0040 +#define RGE_RXCFG 0x0044 +#define RGE_TIMERCNT 0x0048 +#define RGE_EECMD 0x0050 +#define RGE_CFG0 0x0051 +#define RGE_CFG1 0x0052 +#define RGE_CFG2 0x0053 +#define RGE_CFG3 0x0054 +#define RGE_CFG4 0x0055 +#define RGE_CFG5 0x0056 +#define RGE_TDFNR 0x0057 +#define RGE_TIMERINT0 0x0058 +#define RGE_TIMERINT1 0x005c +#define RGE_CSIDR 0x0064 +#define RGE_CSIAR 0x0068 +#define RGE_PHYSTAT 0x006c +#define RGE_PMCH 0x006f +#define RGE_INT_CFG1 0x007a +#define RGE_EPHYAR 0x0080 +#define RGE_TIMERINT2 0x008c +#define RGE_TXSTART 0x0090 +#define RGE_MACOCP 0x00b0 +#define RGE_PHYOCP 0x00b8 +#define RGE_DLLPR 0x00d0 +#define RGE_TWICMD 0x00d2 +#define RGE_MCUCMD 0x00d3 +#define RGE_RXMAXSIZE 0x00da +#define RGE_CPLUSCMD 0x00e0 +#define RGE_IM 0x00e2 +#define RGE_RXDESC_ADDR_LO 0x00e4 +#define RGE_RXDESC_ADDR_HI 0x00e8 +#define RGE_PPSW 0x00f2 +#define RGE_TIMERINT3 0x00f4 +#define RGE_RADMFIFO_PROTECT 0x0402 +#define RGE_INTMITI(i) (0x0a00 + (i) * 4) +#define RGE_RX_MULTIVEC_INTMITI(i) (0x0a00 + (i) * 8) +#define RGE_TX_MULTIVEC_INTMITI(i) (0x0a02 + (i) * 8) +#define RGE_PHYBASE 0x0a40 +#define RGE_IMR_CLR_V2 0x0d00 +#define RGE_ISR_V2 0x0d04 +#define RGE_IMR_SET_V2 0x0d0c +#define RGE_IMR_V4 0x0d10 +#define RGE_ISR_V4 0x0d14 +#define RGE_EPHYAR_EXT_ADDR 0x0ffe +#define RGE_ADDR0 0x19e0 +#define RGE_ADDR1 0x19e4 +#define RGE_TXDESC_ADDR_LO_V2(i) (0x2100 + ((i) - 1) * 8) +#define RGE_TXDESC_ADDR_HI_V2(i) (0x2104 + ((i) - 1) * 8) +#define RGE_RXDESC_ADDR_LO_V2(i) (0x4000 + ((i) - 1) * 8) +#define RGE_RXDESC_ADDR_HI_V2(i) (0x4004 + ((i) - 1) * 8) +#define RGE_RSS_CTRL 0x4500 +#define RGE_RSS_KEY(i) (0x4600 + (i) * 4) +#define RGE_RSS_INDTBL(i) (0x4700 + (i) * 4) +#define RGE_RXQUEUE_CTRL 0x4800 +#define RGE_EEE_TXIDLE_TIMER 0x6048 /* Flags for register RGE_INT_CFG0 */ #define RGE_INT_CFG0_EN 0x01 #define RGE_INT_CFG0_TIMEOUT_BYPASS 0x02 #define RGE_INT_CFG0_MITIGATION_BYPASS 0x04 #define RGE_INT_CFG0_RDU_BYPASS_8126 0x10 +#define RGE_INT_CFG0_AUTO_CLEAR_IMR 0x20 #define RGE_INT_CFG0_AVOID_MISS_INTR 0x40 /* Flags for register RGE_CMD */ @@ -110,6 +125,7 @@ RGE_ISR_SYSTEM_ERR) /* Flags for register RGE_TXCFG */ +#define RGE_TXCFG_NOCLOSE 0x00000040 #define RGE_TXCFG_HWREV 0x7cf00000 /* Flags for register RGE_RXCFG */ @@ -119,7 +135,9 @@ #define RGE_RXCFG_BROAD 0x00000008 #define RGE_RXCFG_RUNT 0x00000010 #define RGE_RXCFG_ERRPKT 0x00000020 +#define RGE_RXCFG_VLANPHYS 0x00008000 #define RGE_RXCFG_VLANSTRIP 0x00c00000 +#define RGE_RXCFG_ENBDESCV1 0x01000000 /* Flags for register RGE_EECMD */ #define RGE_EECMD_WRITECFG 0xc0 @@ -193,12 +211,18 @@ /* Flags for register RGE_CPLUSCMD */ #define RGE_CPLUSCMD_RXCSUM 0x0020 +/* Flags for register RGE_RSS_CTRL */ +#define RGE_RSS_CTRL_TCP_IPV4 0x00000001 +#define RGE_RSS_CTRL_IPV4 0x00000002 +#define RGE_RSS_CTRL_TCP_IPV6 0x00000004 +#define RGE_RSS_CTRL_IPV6 0x00000008 +#define RGE_RSS_CTRL_IPV6_EXT 0x00000010 +#define RGE_RSS_CTRL_TCP_IPV6_EXT 0x00000020 + #define RGE_TX_NSEGS 32 #define RGE_TX_LIST_CNT 1024 #define RGE_RX_LIST_CNT 1024 #define RGE_ALIGN 256 -#define RGE_TX_LIST_SZ (sizeof(struct rge_tx_desc) * RGE_TX_LIST_CNT) -#define RGE_RX_LIST_SZ (sizeof(struct rge_rx_desc) * RGE_RX_LIST_CNT) #define RGE_NEXT_TX_DESC(x) (((x) + 1) % RGE_TX_LIST_CNT) #define RGE_NEXT_RX_DESC(x) (((x) + 1) % RGE_RX_LIST_CNT) #define RGE_ADDR_LO(y) ((uint64_t) (y) & 0xffffffff) @@ -229,6 +253,23 @@ struct rge_tx_desc { #define RGE_TDEXTSTS_TCPCSUM 0x40000000 #define RGE_TDEXTSTS_UDPCSUM 0x80000000 +/* V2 Tx descriptor */ +struct rge_tx_desc_v2 { + uint32_t rge_cmdsts; + uint32_t rge_extsts; + uint64_t rge_addr; +} __packed __aligned(16); + +#define RGE_TDCMDSTS_TCPHO_SHIFT 18 +#define RGE_TDCMDSTS_TCPHO_MAX 112 + +#define RGE_TDEXTSTS_TSOIPV6_V2 0x00000000 +#define RGE_TDEXTSTS_TSOENB_V2 0x00010000 +#define RGE_TDEXTSTS_TSOIPV4_V2 0x20000000 +#define RGE_TDEXTSTS_TSOTCP_V2 0x40000000 +#define RGE_TDEXTSTS_MSS_SHIFT 18 +#define RGE_TDEXTSTS_MAX_MSS 2047 + /* Rx descriptor */ struct rge_rx_desc { union { @@ -240,9 +281,9 @@ struct rge_rx_desc { union { struct { - uint32_t rss; - uint16_t length; - uint16_t hdr_info; + uint32_t rge_rss; + uint16_t rge_length; + uint16_t rge_hdr_info; } rx_qword1; struct { @@ -295,6 +336,41 @@ struct rge_rx_desc { #define RGE_RDEXTSTS_IPV4 0x40000000 #define RGE_RDEXTSTS_IPV6 0x80000000 +/* V2 Rx descriptor */ +struct rge_rx_desc_v2 { + union { + uint64_t rge_addr; + + struct { + uint32_t rge_hdr_info; + uint32_t rge_rss; + } rx_rss; + } qword0; + + struct { + uint32_t rge_extsts; + uint32_t rge_cmdsts; + } rx_qword0; +} __packed __aligned(16); + +#define RGE_RDHDRINFO_RSSTYPE_NONE 0x00000000 +#define RGE_RDHDRINFO_RSSTYPE_MASK 0x30000000 + +#define RGE_RDCMDSTS_TCPCSUMERR_V2 0x00008000 +#define RGE_RDCMDSTS_UDPCSUMERR_V2 0x00010000 +#define RGE_RDCMDSTS_IPCSUMERR_V2 0x00020000 +#define RGE_RDCMDSTS_TCPPKT_V2 0x00040000 +#define RGE_RDCMDSTS_UDPPKT_V2 0x00080000 +#define RGE_RDCMDSTS_RXERRSUM_V2 0x00400000 +#define RGE_RDCMDSTS_EOF_V2 0x10000000 +#define RGE_RDCMDSTS_SOF_V2 0x20000000 + +enum { + CMDSTS_EOF, + CMDSTS_RXERRSUM, + CMDSTS_SOF +}; + /* * Statistics counter structure */ @@ -332,10 +408,12 @@ struct rge_tx { int rge_txq_prodidx; int rge_txq_considx; + struct ifqueue *rge_tx_ifq; bus_dma_segment_t rge_tx_listseg; int rge_tx_listnseg; bus_dmamap_t rge_tx_list_map; struct rge_tx_desc *rge_tx_list; + struct rge_tx_desc_v2 *rge_tx_list_v2; }; struct rge_rx { @@ -343,11 +421,13 @@ struct rge_rx { int rge_rxq_prodidx; int rge_rxq_considx; + struct ifiqueue *rge_rx_ifiq; struct if_rxring rge_rx_ring; bus_dma_segment_t rge_rx_listseg; int rge_rx_listnseg; bus_dmamap_t rge_rx_list_map; struct rge_rx_desc *rge_rx_list; + struct rge_rx_desc_v2 *rge_rx_list_v2; struct mbuf *rge_head; struct mbuf **rge_tail; @@ -356,19 +436,31 @@ struct rge_rx { struct rge_queues { struct rge_softc *q_sc; void *q_ihc; + void *q_tx_ihc; int q_index; + int q_tx_index; char q_name[16]; - pci_intr_handle_t q_ih; + char q_tx_name[16]; struct rge_tx q_tx; struct rge_rx q_rx; + struct task q_task; }; +#define RGE_MAX_VECTORS_8127 8 + +#define RGE_TX_VECTOR_8127(i) (8 + (i)) +#define RGE_LINK_VECTOR_8127 29 +#define RGE_MIN_MSIX_VECTORS_8127 30 + +#define RGE_RSS_KEY_SIZE 40 +#define RGE_RSS_MAX_INDTBL_SIZE 128 + /* Ram version */ #define RGE_MAC_R25D_1_RCODE_VER 0x0027 #define RGE_MAC_R25D_2_RCODE_VER 0x0031 #define RGE_MAC_R26_1_RCODE_VER 0x0033 #define RGE_MAC_R26_2_RCODE_VER 0x0060 -#define RGE_MAC_R27_RCODE_VER 0x0036 +#define RGE_MAC_R27_RCODE_VER 0x0051 #define RGE_MAC_R25_RCODE_VER 0x0b33 #define RGE_MAC_R25B_RCODE_VER 0x0b99 @@ -380,7 +472,8 @@ enum rge_mac_type { MAC_R25D_2, MAC_R26_1, MAC_R26_2, - MAC_R27 + MAC_R27, + MAC_R27ATF }; #define RGE_TYPE_R25D(sc) \ @@ -389,9 +482,16 @@ enum rge_mac_type { #define RGE_TYPE_R26(sc) \ ((sc)->rge_type == MAC_R26_1 || (sc)->rge_type == MAC_R26_2) +#define RGE_TYPE_R27(sc) \ + ((sc)->rge_type == MAC_R27 || (sc)->rge_type == MAC_R27ATF) + #define RGE_TIMEOUT 100 +#define RGE_TIMER_VALUE 19 + +#define RGE_RSS_KEY_SIZE 40 +#define RGE_RSS_MAX_INDTBL_SIZE 128 -#define RGE_JUMBO_FRAMELEN 9216 +#define RGE_JUMBO_FRAMELEN 16384 #define RGE_JUMBO_MTU \ (RGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - \ ETHER_VLAN_ENCAP_LEN) @@ -415,19 +515,24 @@ struct rge_softc { pci_chipset_tag_t sc_pc; pcitag_t sc_tag; struct ifmedia sc_media; /* media info */ + struct intrmap *sc_intrmap; enum rge_mac_type rge_type; - struct rge_queues *sc_queues; - unsigned int sc_nqueues; + uint16_t rge_min_msix; - struct task sc_task; + struct rge_queues *sc_queues; + int sc_nqueues; + int sc_ntxqs; + uint32_t sc_linkvec; struct timeout sc_timeout; /* tick timeout */ uint64_t rge_mcodever; uint16_t rge_rcodever; uint32_t rge_flags; -#define RGE_FLAG_MSI 0x00000001 +#define RGE_FLAG_DESCV2 0x00000001 +#define RGE_FLAG_MSI 0x00000002 +#define RGE_FLAG_MULTIVEC 0x00000004 uint32_t rge_intrs; int rge_timerintr; @@ -884,13 +989,66 @@ static const uint16_t rtl8127_mac_bps_re 0xf84c, 0xf84e, 0xf850, 0xf852, 0xf854, 0xf856, 0xf858, 0xf85a, 0xf85c, 0xf85e, 0xf860, 0xf862, 0xf864, 0xf866, 0xf868, 0xf86a, 0xf86c, 0xf86e, 0xf870, 0xf872, 0xf874, - 0xf876, 0xf878, 0xf87a, 0xf87c + 0xf876, 0xf878, 0xf87a, 0xf87c, 0xf87e, 0xf880, 0xf882, + 0xf884, 0xf886, 0xf888, 0xf88a, 0xf88c, 0xf88e, 0xf890, + 0xf892, 0xf894, 0xf896, 0xf898, 0xf89a, 0xf89c, 0xf89e, + 0xf8a0, 0xf8a2, 0xf8a4, 0xf8a6, 0xf8a8, 0xf8aa, 0xf8ac, + 0xf8ae, 0xf8b0, 0xf8b2, 0xf8b4, 0xf8b6, 0xf8b8, 0xf8ba, + 0xf8bc, 0xf8be, 0xf8c0, 0xf8c2, 0xf8c4, 0xf8c6, 0xf8c8, + 0xf8ca, 0xf8cc, 0xf8ce, 0xf8d0, 0xf8d2, 0xf8d4, 0xf8d6, + 0xf8d8, 0xf8da, 0xf8dc, 0xf8de, 0xf8e0, 0xf8e2, 0xf8e4, + 0xf8e6, 0xf8e8, 0xf8ea, 0xf8ec, 0xf8ee, 0xf8f0, 0xf8f2, + 0xf8f4, 0xf8f6, 0xf8f8, 0xf8fa, 0xf8fc, 0xf8fe, 0xf900, + 0xf902, 0xf904, 0xf906, 0xf908, 0xf90a, 0xf90c, 0xf90e, + 0xf910, 0xf912, 0xf914, 0xf916, 0xf918, 0xf91a, 0xf91c, + 0xf91e, 0xf920, 0xf922, 0xf924, 0xf926, 0xf928, 0xf92a, + 0xf92c, 0xf92e, 0xf930, 0xf932, 0xf934, 0xf936, 0xf938, + 0xf93a, 0xf93c, 0xf93e, 0xf940, 0xf942, 0xf944, 0xf946, + 0xf948, 0xf94a, 0xf94c, 0xf94e, 0xf950, 0xf952, 0xf954, + 0xf956, 0xf958, 0xf95a, 0xf95c, 0xf95e, 0xf960, 0xf962, + 0xf964, 0xf966, 0xf968, 0xf96a, 0xf96c, 0xf96e, 0xf970, + 0xf972, 0xf974, 0xf976, 0xf978, 0xf97a, 0xf97c, 0xf97e, + 0xf980, 0xf982, 0xf984, 0xf986, 0xf988, 0xf98a, 0xf98c, + 0xf98e, 0xf990, 0xf992, 0xf994, 0xf996, 0xf998, 0xf99a, + 0xf99c, 0xf99e, 0xf9a0, 0xf9a2, 0xf9a4, 0xf9a6, 0xf9a8, + 0xf9aa, 0xf9ac, 0xf9ae, 0xf9b0, 0xf9b2, 0xf9b4, 0xf9b6, + 0xf9b8, 0xf9ba, 0xf9bc, 0xf9be, 0xf9c0, 0xf9c2, 0xf9c4, + 0xf9c6, 0xf9c8, 0xf9ca, 0xf9cc, 0xf9ce, 0xf9d0, 0xf9d2, + 0xf9d4, 0xf9d6, 0xf9d8, 0xf9da, 0xf9dc, 0xf9de, 0xf9e0, + 0xf9e2, 0xf9e4, 0xf9e6, 0xf9e8, 0xf9ea, 0xf9ec, 0xf9ee, + 0xf9f0, 0xf9f2, 0xf9f4, 0xf9f6, 0xf9f8, 0xf9fa, 0xf9fc, + 0xf9fe, 0xf800, 0xf802, 0xf804, 0xf806, 0xf808, 0xf80a, + 0xf80c, 0xf80e, 0xf810, 0xf812, 0xf814, 0xf816, 0xf818, + 0xf81a, 0xf81c, 0xf81e, 0xf820, 0xf822, 0xf824, 0xf826, + 0xf828, 0xf82a, 0xf82c, 0xf82e, 0xf830, 0xf832, 0xf834, + 0xf836, 0xf838, 0xf83a, 0xf83c, 0xf83e, 0xf840, 0xf842, + 0xf844, 0xf846, 0xf848, 0xf84a, 0xf84c, 0xf84e, 0xf850, + 0xf852, 0xf854, 0xf856, 0xf858, 0xf85a, 0xf85c, 0xf85e, + 0xf860, 0xf862, 0xf864, 0xf866, 0xf868, 0xf86a, 0xf86c, + 0xf86e, 0xf870, 0xf872, 0xf874, 0xf876, 0xf878, 0xf87a, + 0xf87c, 0xf87e, 0xf880, 0xf882, 0xf884, 0xf886, 0xf888, + 0xf88a, 0xf88c, 0xf88e, 0xf890, 0xf892, 0xf894, 0xf896, + 0xf898, 0xf89a, 0xf89c, 0xf89e, 0xf8a0, 0xf8a2, 0xf8a4, + 0xf8a6, 0xf8a8, 0xf8aa, 0xf8ac, 0xf8ae, 0xf8b0, 0xf8b2, + 0xf8b4, 0xf8b6, 0xf8b8, 0xf8ba, 0xf8bc, 0xf8be, 0xf8c0, + 0xf8c2, 0xf8c4, 0xf8c6, 0xf8c8, 0xf8ca, 0xf8cc, 0xf8ce, + 0xf8d0, 0xf8d2, 0xf8d4, 0xf8d6, 0xf8d8, 0xf8da, 0xf8dc, + 0xf8de, 0xf8e0, 0xf8e2, 0xf8e4, 0xf8e6, 0xf8e8, 0xf8ea, + 0xf8ec, 0xf8ee, 0xf8f0, 0xf8f2, 0xf8f4, 0xf8f6, 0xf8f8, + 0xf8fa, 0xf8fc, 0xf8fe, 0xf900, 0xf902, 0xf904, 0xf906, + 0xf908, 0xf90a, 0xf90c, 0xf90e, 0xf910, 0xf912, 0xf914, + 0xf916, 0xf918, 0xf91a, 0xf91c, 0xf91e, 0xf920, 0xf922, + 0xf924, 0xf926, 0xf928, 0xf92a, 0xf92c, 0xf92e, 0xf930, + 0xf932, 0xf934, 0xf936, 0xf938, 0xf93a, 0xf93c, 0xf93e, + 0xf940, 0xf942, 0xf944, 0xf946, 0xf948, 0xf94a, 0xf94c, + 0xf94e, 0xf950, 0xf952, 0xf954, 0xf956, 0xf958, 0xf95a, + 0xf95c, 0xf95e, 0xf960, 0xf962, 0xf964, 0xf966, 0xf968 }; static const uint16_t rtl8127_mac_bps_vals[] = { 0xe010, 0xe023, 0xe036, 0xe049, 0xe05c, 0xe075, 0xe0b1, - 0xe117, 0xe11b, 0xe11d, 0xe11f, 0xe121, 0xe123, 0xe125, - 0xe127, 0xe129, 0x7020, 0xb405, 0xb404, 0xc50f, 0x74a0, + 0xe117, 0xe11b, 0xe1f7, 0xe1f9, 0xe297, 0xe299, 0xe29b, + 0xe29d, 0xe29f, 0x7020, 0xb405, 0xb404, 0xc50f, 0x74a0, 0xc50e, 0x4025, 0xf005, 0x4850, 0x4025, 0xf002, 0xe002, 0x4809, 0xb004, 0xb005, 0xc502, 0xbd00, 0x1522, 0xd006, 0x0004, 0x7760, 0xb405, 0xb404, 0xc50f, 0x74a0, 0xc50e, @@ -929,11 +1087,64 @@ static const uint16_t rtl8127_mac_bps_va 0xb005, 0xb006, 0xb007, 0x2125, 0xc102, 0xb900, 0x1a6c, 0xd410, 0xc000, 0xe86c, 0xb600, 0xb800, 0xb40a, 0xe024, 0x5a00, 0x5a81, 0x0073, 0x5a80, 0x0042, 0x0001, 0xc104, - 0xc202, 0xba00, 0x1a2e, 0xc896, 0xc302, 0xbb00, 0x0000, - 0xc002, 0xb800, 0x0000, 0xc002, 0xb800, 0x0000, 0xc502, - 0xbd00, 0x0000, 0xc102, 0xb900, 0x0000, 0xc102, 0xb900, - 0x0000, 0xc602, 0xbe00, 0x0000, 0xc602, 0xbe00, 0x0000, - 0x6961, 0x0019, 0x050c, 0x140c + 0xc202, 0xba00, 0x1a2e, 0xc896, 0xb400, 0xb401, 0xb402, + 0xb403, 0xb404, 0xb405, 0xb406, 0xb407, 0xc11f, 0xc21f, + 0x9a24, 0xc21b, 0x9a26, 0xe83b, 0x7320, 0x7422, 0xc010, + 0x7200, 0x4822, 0x9a00, 0x7218, 0x4822, 0x9a18, 0x7206, + 0x4822, 0x9a06, 0x720c, 0x49c0, 0xf00d, 0x4822, 0x9a0c, + 0xe00c, 0xdc46, 0xd40c, 0xe008, 0xdead, 0xde20, 0x0012, + 0x3d02, 0xe8e0, 0x0168, 0x48a2, 0x9a0c, 0x49cf, 0xf058, + 0x1301, 0xf00a, 0x1302, 0xf00d, 0x1303, 0xf01b, 0x1304, + 0xf01f, 0x1305, 0xf024, 0xe043, 0xe858, 0xc7ec, 0xe863, + 0xe893, 0xe048, 0xe853, 0xc7e7, 0x4878, 0xe85d, 0xe88d, + 0xe042, 0xe8e0, 0xf180, 0xbd02, 0x8ffe, 0xc000, 0xc1df, + 0x6227, 0x49a6, 0xf1fd, 0xff80, 0xe843, 0xc7d7, 0x4879, + 0xe84d, 0xe87d, 0xe032, 0xe83d, 0xc7d1, 0x4878, 0x4879, + 0xe846, 0xe876, 0xe02b, 0xc5c8, 0x76a0, 0x4868, 0x9ea0, + 0xc5c3, 0x71a0, 0xc5e7, 0x70a0, 0xc2e1, 0x9940, 0x9842, + 0xc1df, 0x9944, 0xc1de, 0x9946, 0xefdf, 0x71a2, 0x70a4, + 0xc2d7, 0x9940, 0x9842, 0xc16c, 0x9944, 0xc1d4, 0x9946, + 0xefd5, 0xc5ae, 0x76a0, 0x48e8, 0x9ea0, 0xe856, 0xe00b, + 0xc6a9, 0xc2c8, 0x9e40, 0x9e42, 0xc1c6, 0x9944, 0xc1c5, + 0x9946, 0xefc6, 0xe84b, 0xb007, 0xb006, 0xb005, 0xb004, + 0xb003, 0xb002, 0xb001, 0xb000, 0x1100, 0xc202, 0xba00, + 0x1a86, 0xc694, 0xe807, 0x1d00, 0x9dc0, 0xc5b2, 0x9dc2, + 0xe802, 0xff80, 0xc18c, 0x7222, 0x49ae, 0xf1fd, 0xff80, + 0xc687, 0x9fc2, 0xeff9, 0x70c0, 0x0702, 0x9fc2, 0xeff5, + 0x71c0, 0xc235, 0x9940, 0x9842, 0xc19c, 0x9944, 0xc12e, + 0x9946, 0xef9c, 0x0701, 0x9fc2, 0xefe9, 0x70c0, 0x0704, + 0x9fc2, 0xefe5, 0x71c0, 0xc225, 0x9940, 0x9842, 0xc123, + 0x9944, 0xc11e, 0x9946, 0xef8c, 0x071a, 0x9fc2, 0xefd9, + 0x70c0, 0x0728, 0x9fc2, 0xefd5, 0x71c0, 0xc215, 0x9940, + 0x9842, 0xc114, 0x9944, 0xc10e, 0x9946, 0xef7c, 0xff80, + 0x48cf, 0xc20b, 0x9b40, 0x9c42, 0xc107, 0x9944, 0xc104, + 0x9946, 0xef72, 0xff80, 0xbd02, 0xf168, 0xe8e0, 0xf184, + 0xf188, 0xc502, 0xbd00, 0x0000, 0xb400, 0xb401, 0xb402, + 0xb403, 0xc079, 0xc377, 0x7160, 0x9906, 0xc376, 0xe87c, + 0xc073, 0x9900, 0x1906, 0xc371, 0xe884, 0xc170, 0xc370, + 0xe881, 0x1908, 0xc36b, 0xe87e, 0xc36c, 0xe86f, 0x1a88, + 0x44ca, 0xe879, 0xc367, 0x4833, 0xe869, 0x4816, 0xe874, + 0xc362, 0x4838, 0xe864, 0x1a88, 0x44ca, 0xe86e, 0xc35c, + 0x4838, 0x4833, 0xe85d, 0x4816, 0xe868, 0xc357, 0xe859, + 0x1a88, 0x44ca, 0xe863, 0xc352, 0x4833, 0xe853, 0x4816, + 0xe85e, 0xc34d, 0x4838, 0xe84e, 0x1a88, 0x44ca, 0xe858, + 0xc347, 0x4838, 0x4833, 0xe847, 0x4816, 0xe852, 0xc342, + 0xe843, 0x1a58, 0x44ca, 0xe84d, 0xc33d, 0x4833, 0xe83d, + 0x4816, 0xe848, 0xc338, 0x4838, 0xe838, 0x1a58, 0x44ca, + 0xe842, 0xc332, 0x4838, 0x4833, 0xe831, 0x4816, 0xe83c, + 0xc32d, 0xe82d, 0x1a58, 0x44ca, 0xe837, 0xc328, 0x4833, + 0xe827, 0x4816, 0xe832, 0xc323, 0x4838, 0xe822, 0x1a58, + 0x44ca, 0xe82c, 0xc31d, 0x4838, 0x4833, 0xe81b, 0x4816, + 0xe826, 0xc010, 0x7100, 0xc30f, 0xe822, 0xc00c, 0x7106, + 0xc309, 0x9960, 0xb003, 0xb002, 0xb001, 0xb000, 0xc402, + 0xbc00, 0x15b0, 0xde20, 0xdd26, 0x0ffe, 0x0000, 0x6f00, + 0x8086, 0x8486, 0x8886, 0x8c86, 0xc0f7, 0x7202, 0x49ae, + 0xf1fd, 0x44d3, 0x4413, 0x48af, 0x9a02, 0x7202, 0x49ae, + 0xf1fe, 0x7100, 0xff80, 0xc0ea, 0x7202, 0x49ae, 0xf1fd, + 0x9900, 0x44d3, 0x4413, 0x482f, 0x9a02, 0x7202, 0x49ae, + 0xf1fe, 0xff80, 0xc502, 0xbd00, 0x0000, 0xc102, 0xb900, + 0x0000, 0xc102, 0xb900, 0x0000, 0xc602, 0xbe00, 0x0000, + 0xc602, 0xbe00, 0x0000, 0x6961, 0x0019, 0x0a1e, 0x0f2a }; static const struct rge_mac_bps rtl8127_mac_bps = { @@ -4850,598 +5061,1382 @@ static const struct { { 0xa436, 0xa090 }, { 0xa438, 0x00ff }, { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, - { 0xa438, 0x1800 }, { 0xa438, 0x801d }, { 0xa438, 0x1800 }, - { 0xa438, 0x803b }, { 0xa438, 0x1800 }, { 0xa438, 0x8087 }, - { 0xa438, 0x1800 }, { 0xa438, 0x808e }, { 0xa438, 0x1800 }, - { 0xa438, 0x809d }, { 0xa438, 0x1800 }, { 0xa438, 0x80b7 }, - { 0xa438, 0x1800 }, { 0xa438, 0x80c4 }, { 0xa438, 0xd1bc }, + { 0xa438, 0x1800 }, { 0xa438, 0x8663 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8681 }, { 0xa438, 0x1800 }, { 0xa438, 0x86cd }, + { 0xa438, 0x1800 }, { 0xa438, 0x86d4 }, { 0xa438, 0x1800 }, + { 0xa438, 0x86e3 }, { 0xa438, 0x1800 }, { 0xa438, 0x8944 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8951 }, { 0xa438, 0xd1bc }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, { 0xa438, 0xd700 }, - { 0xa438, 0x273d }, { 0xa438, 0x801b }, { 0xa438, 0x1800 }, - { 0xa438, 0x07d1 }, { 0xa438, 0x1800 }, { 0xa438, 0x080e }, - { 0xa438, 0xd700 }, { 0xa438, 0x37c9 }, { 0xa438, 0x8032 }, - { 0xa438, 0x33a9 }, { 0xa438, 0x802a }, { 0xa438, 0xd705 }, - { 0xa438, 0x4084 }, { 0xa438, 0xd1f4 }, { 0xa438, 0xd048 }, - { 0xa438, 0xf013 }, { 0xa438, 0xd1b7 }, { 0xa438, 0xd04b }, - { 0xa438, 0xf010 }, { 0xa438, 0xd705 }, { 0xa438, 0x4084 }, - { 0xa438, 0xd1f4 }, { 0xa438, 0xd048 }, { 0xa438, 0xf00b }, - { 0xa438, 0xd1b7 }, { 0xa438, 0xd04b }, { 0xa438, 0xf008 }, - { 0xa438, 0xd705 }, { 0xa438, 0x4084 }, { 0xa438, 0xd1f4 }, - { 0xa438, 0xd048 }, { 0xa438, 0xf003 }, { 0xa438, 0xd1b7 }, - { 0xa438, 0xd04b }, { 0xa438, 0x1800 }, { 0xa438, 0x14cc }, - { 0xa438, 0xd700 }, { 0xa438, 0x2b59 }, { 0xa438, 0x803f }, - { 0xa438, 0xf003 }, { 0xa438, 0x1800 }, { 0xa438, 0x118f }, - { 0xa438, 0x6060 }, { 0xa438, 0x1800 }, { 0xa438, 0x1167 }, - { 0xa438, 0xd700 }, { 0xa438, 0x60c7 }, { 0xa438, 0xd704 }, - { 0xa438, 0x609f }, { 0xa438, 0xd705 }, { 0xa438, 0x4043 }, - { 0xa438, 0xf003 }, { 0xa438, 0x1800 }, { 0xa438, 0x1150 }, + { 0xa438, 0x273d }, { 0xa438, 0x8056 }, { 0xa438, 0xd700 }, + { 0xa438, 0x37c9 }, { 0xa438, 0x802e }, { 0xa438, 0x33a9 }, + { 0xa438, 0x8026 }, { 0xa438, 0xd702 }, { 0xa438, 0x6099 }, + { 0xa438, 0xd1b7 }, { 0xa438, 0xd05c }, { 0xa438, 0xf013 }, + { 0xa438, 0xd1b7 }, { 0xa438, 0xd05c }, { 0xa438, 0xf010 }, + { 0xa438, 0xd702 }, { 0xa438, 0x6099 }, { 0xa438, 0xd1b7 }, + { 0xa438, 0xd05c }, { 0xa438, 0xf00b }, { 0xa438, 0xd1b7 }, + { 0xa438, 0xd05c }, { 0xa438, 0xf008 }, { 0xa438, 0xd702 }, + { 0xa438, 0x6099 }, { 0xa438, 0xd199 }, { 0xa438, 0xd05d }, + { 0xa438, 0xf003 }, { 0xa438, 0xd199 }, { 0xa438, 0xd05d }, + { 0xa438, 0xd700 }, { 0xa438, 0x37c9 }, { 0xa438, 0x804a }, + { 0xa438, 0x33a9 }, { 0xa438, 0x8042 }, { 0xa438, 0xd702 }, + { 0xa438, 0x6099 }, { 0xa438, 0xd1bf }, { 0xa438, 0xd06d }, + { 0xa438, 0xf013 }, { 0xa438, 0xd1e5 }, { 0xa438, 0xd06d }, + { 0xa438, 0xf010 }, { 0xa438, 0xd702 }, { 0xa438, 0x6099 }, + { 0xa438, 0xd1ec }, { 0xa438, 0xd06d }, { 0xa438, 0xf00b }, + { 0xa438, 0xd1bf }, { 0xa438, 0xd06d }, { 0xa438, 0xf008 }, + { 0xa438, 0xd702 }, { 0xa438, 0x6099 }, { 0xa438, 0xd199 }, + { 0xa438, 0xd06e }, { 0xa438, 0xf003 }, { 0xa438, 0xd199 }, + { 0xa438, 0xd06e }, { 0xa438, 0xd703 }, { 0xa438, 0x6090 }, + { 0xa438, 0xd41a }, { 0xa438, 0x1000 }, { 0xa438, 0x1cc8 }, + { 0xa438, 0xd408 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cc8 }, + { 0xa438, 0xcd31 }, { 0xa438, 0xd700 }, { 0xa438, 0x2fa9 }, + { 0xa438, 0x8061 }, { 0xa438, 0x33c9 }, { 0xa438, 0x8064 }, + { 0xa438, 0x6117 }, { 0xa438, 0xf00a }, { 0xa438, 0xd141 }, + { 0xa438, 0xd043 }, { 0xa438, 0xf009 }, { 0xa438, 0xd121 }, + { 0xa438, 0xd043 }, { 0xa438, 0xf006 }, { 0xa438, 0xd122 }, + { 0xa438, 0xd042 }, { 0xa438, 0xf003 }, { 0xa438, 0xd181 }, + { 0xa438, 0xd043 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, { 0xa438, 0xd700 }, + { 0xa438, 0x2969 }, { 0xa438, 0x80da }, { 0xa438, 0xd700 }, + { 0xa438, 0x6ccb }, { 0xa438, 0xd700 }, { 0xa438, 0x6d67 }, + { 0xa438, 0x800a }, { 0xa438, 0x81a0 }, { 0xa438, 0x8312 }, + { 0xa438, 0x8480 }, { 0xa438, 0x0c86 }, { 0xa438, 0x0680 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x8702 }, - { 0xa438, 0x8011 }, { 0xa438, 0x9503 }, { 0xa438, 0x800a }, - { 0xa438, 0x81a0 }, { 0xa438, 0x8302 }, { 0xa438, 0x8480 }, - { 0xa438, 0x8686 }, { 0xa438, 0xcde0 }, { 0xa438, 0xd1ff }, - { 0xa438, 0xd049 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, - { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, { 0xa438, 0xd705 }, - { 0xa438, 0x417e }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, - { 0xa438, 0xa011 }, { 0xa438, 0x9503 }, { 0xa438, 0xd1c8 }, - { 0xa438, 0xd045 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, - { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, { 0xa438, 0x0c03 }, - { 0xa438, 0x1502 }, { 0xa438, 0xa702 }, { 0xa438, 0x9503 }, - { 0xa438, 0xa00a }, { 0xa438, 0xa1a0 }, { 0xa438, 0xa480 }, - { 0xa438, 0xa686 }, { 0xa438, 0xd705 }, { 0xa438, 0x605e }, - { 0xa438, 0xa302 }, { 0xa438, 0x9503 }, { 0xa438, 0xd700 }, - { 0xa438, 0x37c9 }, { 0xa438, 0x8083 }, { 0xa438, 0x33a9 }, - { 0xa438, 0x807f }, { 0xa438, 0xd178 }, { 0xa438, 0xd04b }, - { 0xa438, 0x1800 }, { 0xa438, 0x115d }, { 0xa438, 0xd1c8 }, + { 0xa438, 0x9503 }, { 0xa438, 0xd407 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cc8 }, { 0xa438, 0xd703 }, { 0xa438, 0x6090 }, + { 0xa438, 0xd41a }, { 0xa438, 0x1000 }, { 0xa438, 0x1cc8 }, + { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x8380 }, + { 0xa438, 0x9503 }, { 0xa438, 0xd406 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cc8 }, { 0xa438, 0xcd39 }, { 0xa438, 0xd404 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cc8 }, { 0xa438, 0xd700 }, + { 0xa438, 0x60cf }, { 0xa438, 0x60f1 }, { 0xa438, 0x6113 }, + { 0xa438, 0x6135 }, { 0xa438, 0x6157 }, { 0xa438, 0xf00b }, + { 0xa438, 0xce03 }, { 0xa438, 0xf00a }, { 0xa438, 0xce03 }, + { 0xa438, 0xf008 }, { 0xa438, 0xce03 }, { 0xa438, 0xf006 }, + { 0xa438, 0xce03 }, { 0xa438, 0xf004 }, { 0xa438, 0xce03 }, + { 0xa438, 0xf002 }, { 0xa438, 0xce03 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1ce7 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, + { 0xa438, 0x0c07 }, { 0xa438, 0x0c01 }, { 0xa438, 0x8d07 }, + { 0xa438, 0x0cc3 }, { 0xa438, 0x0b40 }, { 0xa438, 0x8d07 }, + { 0xa438, 0x9503 }, { 0xa438, 0xa810 }, { 0xa438, 0xa00a }, + { 0xa438, 0xa302 }, { 0xa438, 0x0ca0 }, { 0xa438, 0x0480 }, + { 0xa438, 0xa684 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0xd706 }, { 0xa438, 0x5fa7 }, { 0xa438, 0xb920 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, { 0xa438, 0xd71f }, + { 0xa438, 0x7fb4 }, { 0xa438, 0x8810 }, { 0xa438, 0x9920 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, { 0xa438, 0xd71f }, + { 0xa438, 0x60e5 }, { 0xa438, 0x5f94 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cd2 }, { 0xa438, 0xd706 }, { 0xa438, 0x5fa7 }, + { 0xa438, 0xfff0 }, { 0xa438, 0xb820 }, { 0xa438, 0xa810 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, { 0xa438, 0xd71f }, + { 0xa438, 0x7fa5 }, { 0xa438, 0x9820 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cd2 }, { 0xa438, 0x1000 }, { 0xa438, 0x1d2b }, + { 0xa438, 0xd706 }, { 0xa438, 0x5f69 }, { 0xa438, 0xf010 }, + { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0xae80 }, + { 0xa438, 0x9503 }, { 0xa438, 0xd700 }, { 0xa438, 0x2b6d }, + { 0xa438, 0x8184 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, + { 0xa438, 0x8380 }, { 0xa438, 0x9503 }, { 0xa438, 0xd406 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cc8 }, { 0xa438, 0xcd32 }, + { 0xa438, 0xd701 }, { 0xa438, 0x6191 }, { 0xa438, 0xa504 }, + { 0xa438, 0xcd3a }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0xd700 }, { 0xa438, 0x6067 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1d2b }, { 0xa438, 0xd701 }, { 0xa438, 0x5f3a }, + { 0xa438, 0x8504 }, { 0xa438, 0xd700 }, { 0xa438, 0x2739 }, + { 0xa438, 0x817a }, { 0xa438, 0xd707 }, { 0xa438, 0x6061 }, + { 0xa438, 0x1800 }, { 0xa438, 0x816c }, { 0xa438, 0xd193 }, + { 0xa438, 0xd047 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1d2b }, { 0xa438, 0xd700 }, + { 0xa438, 0x5f7a }, { 0xa438, 0xd706 }, { 0xa438, 0x5f29 }, + { 0xa438, 0xd700 }, { 0xa438, 0x60cf }, { 0xa438, 0x60f1 }, + { 0xa438, 0x6113 }, { 0xa438, 0x6135 }, { 0xa438, 0x6157 }, + { 0xa438, 0xf00b }, { 0xa438, 0xce06 }, { 0xa438, 0xf00a }, + { 0xa438, 0xce06 }, { 0xa438, 0xf008 }, { 0xa438, 0xce06 }, + { 0xa438, 0xf006 }, { 0xa438, 0xce06 }, { 0xa438, 0xf004 }, + { 0xa438, 0xce06 }, { 0xa438, 0xf002 }, { 0xa438, 0xce06 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1ce7 }, { 0xa438, 0x0c03 }, + { 0xa438, 0x1502 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0b01 }, + { 0xa438, 0x0c3f }, { 0xa438, 0x0c08 }, { 0xa438, 0x8bc0 }, + { 0xa438, 0x9503 }, { 0xa438, 0xd707 }, { 0xa438, 0x409f }, + { 0xa438, 0x4062 }, { 0xa438, 0x8310 }, { 0xa438, 0xf002 }, + { 0xa438, 0xa310 }, { 0xa438, 0xa120 }, { 0xa438, 0xa420 }, + { 0xa438, 0xd193 }, { 0xa438, 0xd048 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cd2 }, { 0xa438, 0x1000 }, { 0xa438, 0x1d2b }, + { 0xa438, 0xd700 }, { 0xa438, 0x5f7a }, { 0xa438, 0xd706 }, + { 0xa438, 0x5f29 }, { 0xa438, 0xd700 }, { 0xa438, 0x60cf }, + { 0xa438, 0x60f1 }, { 0xa438, 0x6113 }, { 0xa438, 0x6135 }, + { 0xa438, 0x6157 }, { 0xa438, 0xf00b }, { 0xa438, 0xce03 }, + { 0xa438, 0xf00a }, { 0xa438, 0xce03 }, { 0xa438, 0xf008 }, + { 0xa438, 0xce03 }, { 0xa438, 0xf006 }, { 0xa438, 0xce03 }, + { 0xa438, 0xf004 }, { 0xa438, 0xce03 }, { 0xa438, 0xf002 }, + { 0xa438, 0xce03 }, { 0xa438, 0x1000 }, { 0xa438, 0x1ce7 }, + { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x0c07 }, + { 0xa438, 0x0c01 }, { 0xa438, 0x9503 }, { 0xa438, 0x8420 }, + { 0xa438, 0x800a }, { 0xa438, 0x8120 }, { 0xa438, 0x8312 }, + { 0xa438, 0x8480 }, { 0xa438, 0x8604 }, { 0xa438, 0xd419 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cc8 }, { 0xa438, 0xd702 }, + { 0xa438, 0x4080 }, { 0xa438, 0xbb20 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8507 }, { 0xa438, 0xa00a }, { 0xa438, 0xa302 }, + { 0xa438, 0xa480 }, { 0xa438, 0xa604 }, { 0xa438, 0xd193 }, + { 0xa438, 0xd047 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1d2b }, { 0xa438, 0xd700 }, + { 0xa438, 0x5f7a }, { 0xa438, 0xd706 }, { 0xa438, 0x5f29 }, + { 0xa438, 0x1800 }, { 0xa438, 0x814f }, { 0xa438, 0x800a }, + { 0xa438, 0x8302 }, { 0xa438, 0x8480 }, { 0xa438, 0x8604 }, + { 0xa438, 0xd405 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cc8 }, + { 0xa438, 0xbb20 }, { 0xa438, 0xa00a }, { 0xa438, 0xa302 }, + { 0xa438, 0xa480 }, { 0xa438, 0xa604 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8507 }, { 0xa438, 0xd405 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cc8 }, { 0xa438, 0xd404 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cc8 }, { 0xa438, 0xd700 }, { 0xa438, 0x2b69 }, + { 0xa438, 0x8184 }, { 0xa438, 0xf06d }, { 0xa438, 0xd700 }, + { 0xa438, 0x60cf }, { 0xa438, 0x60f1 }, { 0xa438, 0x6113 }, + { 0xa438, 0x6135 }, { 0xa438, 0x6157 }, { 0xa438, 0xf00b }, + { 0xa438, 0xce03 }, { 0xa438, 0xf00a }, { 0xa438, 0xce03 }, + { 0xa438, 0xf008 }, { 0xa438, 0xce03 }, { 0xa438, 0xf006 }, + { 0xa438, 0xce03 }, { 0xa438, 0xf004 }, { 0xa438, 0xce03 }, + { 0xa438, 0xf002 }, { 0xa438, 0xce03 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1ce7 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, + { 0xa438, 0x0c07 }, { 0xa438, 0x0c01 }, { 0xa438, 0x0c3f }, + { 0xa438, 0x0d08 }, { 0xa438, 0x9503 }, { 0xa438, 0xa810 }, + { 0xa438, 0xa00a }, { 0xa438, 0xa302 }, { 0xa438, 0x0ca0 }, + { 0xa438, 0x0480 }, { 0xa438, 0xd700 }, { 0xa438, 0x2969 }, + { 0xa438, 0x0960 }, { 0xa438, 0x60a4 }, { 0xa438, 0xd704 }, + { 0xa438, 0x407d }, { 0xa438, 0x8604 }, { 0xa438, 0xf002 }, + { 0xa438, 0xa604 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, + { 0xa438, 0xa340 }, { 0xa438, 0xd700 }, { 0xa438, 0x37cd }, + { 0xa438, 0x81b4 }, { 0xa438, 0x8310 }, { 0xa438, 0x9503 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, { 0xa438, 0xd706 }, + { 0xa438, 0x5fa7 }, { 0xa438, 0xb920 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cd2 }, { 0xa438, 0xd71f }, { 0xa438, 0x7fb4 }, + { 0xa438, 0x8810 }, { 0xa438, 0x9920 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cd2 }, { 0xa438, 0xd71f }, { 0xa438, 0x60e5 }, + { 0xa438, 0x5f94 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0xd706 }, { 0xa438, 0x5fa7 }, { 0xa438, 0xfff0 }, + { 0xa438, 0xb820 }, { 0xa438, 0xa810 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cd2 }, { 0xa438, 0xd71f }, { 0xa438, 0x7fa5 }, + { 0xa438, 0x9820 }, { 0xa438, 0xd700 }, { 0xa438, 0x2d59 }, + { 0xa438, 0x8507 }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, + { 0xa438, 0x8c07 }, { 0xa438, 0x9503 }, { 0xa438, 0xa120 }, + { 0xa438, 0xd700 }, { 0xa438, 0x2969 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}, { 0xa438, 0x0276 }, - { 0xa438, 0x7402 }, { 0xa438, 0x8929 }, { 0xa438, 0xd401 }, - { 0xa438, 0x28d6 }, { 0xa438, 0x0010 }, { 0xa438, 0xd20f }, - { 0xa438, 0xe684 }, { 0xa438, 0x7602 }, { 0xa438, 0x6671 }, - { 0xa438, 0x021f }, { 0xa438, 0xbbff }, { 0xa438, 0xfefd }, - { 0xa438, 0xef95 }, { 0xa438, 0xfdfc }, { 0xa438, 0x04f8 }, - { 0xa438, 0xf9ef }, { 0xa438, 0x59f9 }, { 0xa438, 0xe080 }, - { 0xa438, 0x12ad }, { 0xa438, 0x230c }, { 0xa438, 0xbf72 }, - { 0xa438, 0x9e02 }, { 0xa438, 0x766b }, { 0xa438, 0xbf72 }, - { 0xa438, 0x9502 }, { 0xa438, 0x766b }, { 0xa438, 0xfdef }, - { 0xa438, 0x95fd }, { 0xa438, 0xfc04 }, { 0xa438, 0xbf6e }, - { 0xa438, 0x0602 }, { 0xa438, 0x76b6 }, { 0xa438, 0xef64 }, - { 0xa438, 0xbf6e }, { 0xa438, 0x0902 }, { 0xa438, 0x76b6 }, - { 0xa438, 0x1e64 }, { 0xa438, 0xbf6e }, { 0xa438, 0x0f02 }, - { 0xa438, 0x76b6 }, { 0xa438, 0x1e64 }, { 0xa438, 0xac40 }, - { 0xa438, 0x0ebf }, { 0xa438, 0x7298 }, { 0xa438, 0x0276 }, - { 0xa438, 0xb6e5 }, { 0xa438, 0x8478 }, { 0xa438, 0xa10f }, - { 0xa438, 0x26ae }, { 0xa438, 0x47bf }, { 0xa438, 0x8bf3 }, - { 0xa438, 0x0276 }, { 0xa438, 0xb6ac }, { 0xa438, 0x2802 }, - { 0xa438, 0xae0b }, { 0xa438, 0xbf8b }, { 0xa438, 0xf902 }, - { 0xa438, 0x76b6 }, { 0xa438, 0xe584 }, { 0xa438, 0x78ae }, - { 0xa438, 0x09bf }, { 0xa438, 0x8bf6 }, { 0xa438, 0x0276 }, - { 0xa438, 0xb6e5 }, { 0xa438, 0x8478 }, { 0xa438, 0xa103 }, - { 0xa438, 0x02ae }, { 0xa438, 0x23e0 }, { 0xa438, 0x8474 }, - { 0xa438, 0xe184 }, { 0xa438, 0x75ef }, { 0xa438, 0x64e0 }, - { 0xa438, 0x83fc }, { 0xa438, 0xe183 }, { 0xa438, 0xfdef }, - { 0xa438, 0x7402 }, { 0xa438, 0x75d9 }, { 0xa438, 0xad50 }, - { 0xa438, 0x0ae0 }, { 0xa438, 0x83ec }, { 0xa438, 0xf721 }, - { 0xa438, 0xe483 }, { 0xa438, 0xecae }, { 0xa438, 0x03af }, - { 0xa438, 0x68e4 }, { 0xa438, 0xbf72 }, { 0xa438, 0x9502 }, - { 0xa438, 0x766b }, { 0xa438, 0xe083 }, { 0xa438, 0xebad }, - { 0xa438, 0x2170 }, { 0xa438, 0xbf73 }, { 0xa438, 0x7f02 }, - { 0xa438, 0x766b }, { 0xa438, 0xd700 }, { 0xa438, 0x64bf }, - { 0xa438, 0x73c4 }, { 0xa438, 0x0276 }, { 0xa438, 0xb6a4 }, - { 0xa438, 0x0000 }, { 0xa438, 0x02ae }, { 0xa438, 0x0d87 }, - { 0xa438, 0xa700 }, { 0xa438, 0x00ef }, { 0xa438, 0xe183 }, - { 0xa438, 0xecf7 }, { 0xa438, 0x2ae5 }, { 0xa438, 0x83ec }, - { 0xa438, 0xbf73 }, { 0xa438, 0xbe02 }, { 0xa438, 0x766b }, - { 0xa438, 0xbf73 }, { 0xa438, 0xb802 }, { 0xa438, 0x766b }, - { 0xa438, 0xbf73 }, { 0xa438, 0xc102 }, { 0xa438, 0x766b }, - { 0xa438, 0xbf73 }, { 0xa438, 0xbb02 }, { 0xa438, 0x766b }, - { 0xa438, 0xe084 }, { 0xa438, 0x9ee1 }, { 0xa438, 0x849f }, - { 0xa438, 0xbf72 }, { 0xa438, 0x7d02 }, { 0xa438, 0x7697 }, - { 0xa438, 0xbf72 }, { 0xa438, 0x8002 }, { 0xa438, 0x7697 }, - { 0xa438, 0xbf72 }, { 0xa438, 0x8302 }, { 0xa438, 0x7697 }, - { 0xa438, 0xbf72 }, { 0xa438, 0x8602 }, { 0xa438, 0x7697 }, - { 0xa438, 0xbf72 }, { 0xa438, 0x8902 }, { 0xa438, 0x7674 }, - { 0xa438, 0xbf72 }, { 0xa438, 0x8c02 }, { 0xa438, 0x7674 }, - { 0xa438, 0xbf72 }, { 0xa438, 0x8f02 }, { 0xa438, 0x7674 }, - { 0xa438, 0xbf72 }, { 0xa438, 0x9202 }, { 0xa438, 0x7674 }, - { 0xa438, 0xee84 }, { 0xa438, 0x7700 }, { 0xa438, 0xe080 }, - { 0xa438, 0x44f6 }, { 0xa438, 0x21e4 }, { 0xa438, 0x8044 }, - { 0xa438, 0xaf68 }, { 0xa438, 0xe411 }, { 0xa438, 0xd1a4 }, - { 0xa438, 0x10bc }, { 0xa438, 0x7432 }, { 0xa438, 0xbc74 }, - { 0xa438, 0xbbbf }, { 0xa438, 0x14cc }, { 0xa438, 0xbfaa }, - { 0xa438, 0x00bf }, { 0xa438, 0x9055 }, { 0xa438, 0xbf06 }, - { 0xa438, 0x10bf }, { 0xa438, 0xb876 }, { 0xa438, 0xbe02 }, - { 0xa438, 0x54be }, { 0xa438, 0x0232 }, { 0xa438, 0xbe02 }, - { 0xa438, 0x10be }, { 0xa438, 0x0200 }, { 0xa436, 0x8fe7 }, - { 0xa438, 0x1200 }, { 0xa436, 0x8fe9 }, { 0xa438, 0x1200 }, - { 0xa436, 0x8feb }, { 0xa438, 0x1200 }, { 0xa436, 0x8fed }, - { 0xa438, 0x1200 }, { 0xa436, 0x8fef }, { 0xa438, 0x1200 }, - { 0xa436, 0x8ff1 }, { 0xa438, 0x1200 }, { 0xa436, 0x8ff3 }, - { 0xa438, 0x1200 }, { 0xa436, 0x8ff5 }, { 0xa438, 0x1200 }, - { 0xa436, 0x8ff7 }, { 0xa438, 0x1200 }, { 0xa436, 0x8ff9 }, - { 0xa438, 0x1200 }, { 0xa436, 0x8ffb }, { 0xa438, 0x1200 }, - { 0xa436, 0x8ffd }, { 0xa438, 0x1200 }, { 0xa436, 0xb818 }, - { 0xa438, 0x6602 }, { 0xa436, 0xb81a }, { 0xa438, 0x1f75 }, - { 0xa436, 0xb81c }, { 0xa438, 0x67eb }, { 0xa436, 0xb81e }, - { 0xa438, 0xffff }, { 0xa436, 0xb850 }, { 0xa438, 0xffff }, - { 0xa436, 0xb852 }, { 0xa438, 0xffff }, { 0xa436, 0xb878 }, - { 0xa438, 0xffff }, { 0xa436, 0xb884 }, { 0xa438, 0xffff }, - { 0xa436, 0xb832 }, { 0xa438, 0x0007 }, { 0xb82e, 0x0000 }, - { 0xa436, 0x8023 }, { 0xa438, 0x0000 }, { 0xb820, 0x0000 }, - { 0xb892, 0x0000 }, { 0xb88e, 0xc07c }, { 0xb890, 0x0203 }, - { 0xb890, 0x0304 }, { 0xb890, 0x0405 }, { 0xb890, 0x0607 }, - { 0xb890, 0x0809 }, { 0xb890, 0x0b0d }, { 0xb890, 0x0f11 }, - { 0xb890, 0x1418 }, { 0xb890, 0x1b20 }, { 0xb890, 0x252b }, - { 0xb890, 0x343e }, { 0xb890, 0x4854 }, { 0xb890, 0x6203 }, - { 0xb890, 0x0304 }, { 0xb890, 0x0506 }, { 0xb890, 0x080a }, - { 0xb890, 0x0c0e }, { 0xb890, 0x1216 }, { 0xb890, 0x1b22 }, - { 0xb890, 0x2a34 }, { 0xb890, 0x404f }, { 0xb890, 0x6171 }, - { 0xb890, 0x7884 }, { 0xb890, 0x9097 }, { 0xb890, 0x0203 }, - { 0xb890, 0x0406 }, { 0xb890, 0x080b }, { 0xb890, 0x0e13 }, - { 0xb890, 0x1820 }, { 0xb890, 0x2a39 }, { 0xb890, 0x4856 }, - { 0xb890, 0xe060 }, { 0xb890, 0xe050 }, { 0xb890, 0xd080 }, - { 0xb890, 0x8070 }, { 0xb890, 0x70a0 }, { 0xb890, 0x1000 }, - { 0xb890, 0x60d0 }, { 0xb890, 0xb010 }, { 0xb890, 0xe0b0 }, - { 0xb890, 0x80c0 }, { 0xb890, 0xe000 }, { 0xb890, 0x2020 }, - { 0xb890, 0x1020 }, { 0xb890, 0xe090 }, { 0xb890, 0x80c0 }, - { 0xb890, 0x3020 }, { 0xb890, 0x00e0 }, { 0xb890, 0x40a0 }, - { 0xb890, 0xe020 }, { 0xb890, 0x5060 }, { 0xb890, 0xe0d0 }, - { 0xb890, 0xa000 }, { 0xb890, 0x3030 }, { 0xb890, 0x4070 }, - { 0xb890, 0xe0e0 }, { 0xb890, 0xd080 }, { 0xb890, 0xa010 }, - { 0xb890, 0xe040 }, { 0xb890, 0x80b0 }, { 0xb890, 0x50b0 }, - { 0xb890, 0x2090 }, { 0xb820, 0x0000 } + { 0xa438, 0x8478 }, { 0xa438, 0xa10f }, { 0xa438, 0x26ae }, + { 0xa438, 0x47bf }, { 0xa438, 0x8bf3 }, { 0xa438, 0x0276 }, + { 0xa438, 0xb6ac }, { 0xa438, 0x2802 }, { 0xa438, 0xae0b }, + { 0xa438, 0xbf8b }, { 0xa438, 0xf902 }, { 0xa438, 0x76b6 }, + { 0xa438, 0xe584 }, { 0xa438, 0x78ae }, { 0xa438, 0x09bf }, + { 0xa438, 0x8bf6 }, { 0xa438, 0x0276 }, { 0xa438, 0xb6e5 }, + { 0xa438, 0x8478 }, { 0xa438, 0xa103 }, { 0xa438, 0x02ae }, + { 0xa438, 0x23e0 }, { 0xa438, 0x8474 }, { 0xa438, 0xe184 }, + { 0xa438, 0x75ef }, { 0xa438, 0x64e0 }, { 0xa438, 0x83fc }, + { 0xa438, 0xe183 }, { 0xa438, 0xfdef }, { 0xa438, 0x7402 }, + { 0xa438, 0x75d9 }, { 0xa438, 0xad50 }, { 0xa438, 0x0ae0 }, + { 0xa438, 0x83ec }, { 0xa438, 0xf721 }, { 0xa438, 0xe483 }, + { 0xa438, 0xecae }, { 0xa438, 0x03af }, { 0xa438, 0x68e4 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x9502 }, { 0xa438, 0x766b }, + { 0xa438, 0xe083 }, { 0xa438, 0xebad }, { 0xa438, 0x2170 }, + { 0xa438, 0xbf73 }, { 0xa438, 0x7f02 }, { 0xa438, 0x766b }, + { 0xa438, 0xd700 }, { 0xa438, 0x64bf }, { 0xa438, 0x73c4 }, + { 0xa438, 0x0276 }, { 0xa438, 0xb6a4 }, { 0xa438, 0x0000 }, + { 0xa438, 0x02ae }, { 0xa438, 0x0d87 }, { 0xa438, 0xa700 }, + { 0xa438, 0x00ef }, { 0xa438, 0xe183 }, { 0xa438, 0xecf7 }, + { 0xa438, 0x2ae5 }, { 0xa438, 0x83ec }, { 0xa438, 0xbf73 }, + { 0xa438, 0xbe02 }, { 0xa438, 0x766b }, { 0xa438, 0xbf73 }, + { 0xa438, 0xb802 }, { 0xa438, 0x766b }, { 0xa438, 0xbf73 }, + { 0xa438, 0xc102 }, { 0xa438, 0x766b }, { 0xa438, 0xbf73 }, + { 0xa438, 0xbb02 }, { 0xa438, 0x766b }, { 0xa438, 0xe084 }, + { 0xa438, 0x9ee1 }, { 0xa438, 0x849f }, { 0xa438, 0xbf72 }, + { 0xa438, 0x7d02 }, { 0xa438, 0x7697 }, { 0xa438, 0xbf72 }, + { 0xa438, 0x8002 }, { 0xa438, 0x7697 }, { 0xa438, 0xbf72 }, + { 0xa438, 0x8302 }, { 0xa438, 0x7697 }, { 0xa438, 0xbf72 }, + { 0xa438, 0x8602 }, { 0xa438, 0x7697 }, { 0xa438, 0xbf72 }, + { 0xa438, 0x8902 }, { 0xa438, 0x7674 }, { 0xa438, 0xbf72 }, + { 0xa438, 0x8c02 }, { 0xa438, 0x7674 }, { 0xa438, 0xbf72 }, + { 0xa438, 0x8f02 }, { 0xa438, 0x7674 }, { 0xa438, 0xbf72 }, + { 0xa438, 0x9202 }, { 0xa438, 0x7674 }, { 0xa438, 0xee84 }, + { 0xa438, 0x7700 }, { 0xa438, 0xe080 }, { 0xa438, 0x44f6 }, + { 0xa438, 0x21e4 }, { 0xa438, 0x8044 }, { 0xa438, 0xaf68 }, + { 0xa438, 0xe411 }, { 0xa438, 0xd1a4 }, { 0xa438, 0x10bc }, + { 0xa438, 0x7432 }, { 0xa438, 0xbc74 }, { 0xa438, 0xbbbf }, + { 0xa438, 0x14cc }, { 0xa438, 0xbfaa }, { 0xa438, 0x00bf }, + { 0xa438, 0x9055 }, { 0xa438, 0xbf06 }, { 0xa438, 0x10bf }, + { 0xa438, 0xb876 }, { 0xa438, 0xbe02 }, { 0xa438, 0x54be }, + { 0xa438, 0x0232 }, { 0xa438, 0xbe02 }, { 0xa438, 0x10be }, + { 0xa438, 0x0200 }, { 0xa436, 0x8fe7 }, { 0xa438, 0x1200 }, + { 0xa436, 0x8fe9 }, { 0xa438, 0x1200 }, { 0xa436, 0x8feb }, + { 0xa438, 0x1200 }, { 0xa436, 0x8fed }, { 0xa438, 0x1200 }, + { 0xa436, 0x8fef }, { 0xa438, 0x1200 }, { 0xa436, 0x8ff1 }, + { 0xa438, 0x1200 }, { 0xa436, 0x8ff3 }, { 0xa438, 0x1200 }, + { 0xa436, 0x8ff5 }, { 0xa438, 0x1200 }, { 0xa436, 0x8ff7 }, + { 0xa438, 0x1200 }, { 0xa436, 0x8ff9 }, { 0xa438, 0x1200 }, + { 0xa436, 0x8ffb }, { 0xa438, 0x1200 }, { 0xa436, 0x8ffd }, + { 0xa438, 0x1200 }, { 0xa436, 0xb818 }, { 0xa438, 0x6602 }, + { 0xa436, 0xb81a }, { 0xa438, 0x1f75 }, { 0xa436, 0xb81c }, + { 0xa438, 0x67eb }, { 0xa436, 0xb81e }, { 0xa438, 0xffff }, + { 0xa436, 0xb850 }, { 0xa438, 0xffff }, { 0xa436, 0xb852 }, + { 0xa438, 0xffff }, { 0xa436, 0xb878 }, { 0xa438, 0xffff }, + { 0xa436, 0xb884 }, { 0xa438, 0xffff }, { 0xa436, 0xb832 }, + { 0xa438, 0x0007 }, { 0xb82e, 0x0000 }, { 0xa436, 0x8023 }, + { 0xa438, 0x0000 }, { 0xb820, 0x0000 }, { 0xb892, 0x0000 }, + { 0xb88e, 0xc07c }, { 0xb890, 0x0203 }, { 0xb890, 0x0304 }, + { 0xb890, 0x0405 }, { 0xb890, 0x0607 }, { 0xb890, 0x0809 }, + { 0xb890, 0x0b0d }, { 0xb890, 0x0f11 }, { 0xb890, 0x1418 }, + { 0xb890, 0x1b20 }, { 0xb890, 0x252b }, { 0xb890, 0x343e }, + { 0xb890, 0x4854 }, { 0xb890, 0x6203 }, { 0xb890, 0x0304 }, + { 0xb890, 0x0506 }, { 0xb890, 0x080a }, { 0xb890, 0x0c0e }, + { 0xb890, 0x1216 }, { 0xb890, 0x1b22 }, { 0xb890, 0x2a34 }, + { 0xb890, 0x404f }, { 0xb890, 0x6171 }, { 0xb890, 0x7884 }, + { 0xb890, 0x9097 }, { 0xb890, 0x0203 }, { 0xb890, 0x0406 }, + { 0xb890, 0x080b }, { 0xb890, 0x0e13 }, { 0xb890, 0x1820 }, + { 0xb890, 0x2a39 }, { 0xb890, 0x4856 }, { 0xb890, 0xe060 }, + { 0xb890, 0xe050 }, { 0xb890, 0xd080 }, { 0xb890, 0x8070 }, + { 0xb890, 0x70a0 }, { 0xb890, 0x1000 }, { 0xb890, 0x60d0 }, + { 0xb890, 0xb010 }, { 0xb890, 0xe0b0 }, { 0xb890, 0x80c0 }, + { 0xb890, 0xe000 }, { 0xb890, 0x2020 }, { 0xb890, 0x1020 }, + { 0xb890, 0xe090 }, { 0xb890, 0x80c0 }, { 0xb890, 0x3020 }, + { 0xb890, 0x00e0 }, { 0xb890, 0x40a0 }, { 0xb890, 0xe020 }, + { 0xb890, 0x5060 }, { 0xb890, 0xe0d0 }, { 0xb890, 0xa000 }, + { 0xb890, 0x3030 }, { 0xb890, 0x4070 }, { 0xb890, 0xe0e0 }, + { 0xb890, 0xd080 }, { 0xb890, 0xa010 }, { 0xb890, 0xe040 }, + { 0xb890, 0x80b0 }, { 0xb890, 0x50b0 }, { 0xb890, 0x2090 }, + { 0xb88e, 0xc110 }, { 0xb890, 0xe8f4 }, { 0xb890, 0xf4f4 }, + { 0xb88e, 0xc14e }, { 0xb890, 0x26ef }, { 0xb890, 0xefef }, + { 0xb88e, 0xc374 }, { 0xb890, 0x00fa }, { 0xb890, 0x008c }, + { 0xb890, 0x03d2 }, { 0xb890, 0x0373 }, { 0xb890, 0x03b9 }, + { 0xb890, 0x0006 }, { 0xb890, 0x0013 }, { 0xb890, 0x03fe }, + { 0xb890, 0x03de }, { 0xb890, 0x0008 }, { 0xb890, 0x0008 }, + { 0xb890, 0x000d }, { 0xb890, 0x03f3 }, { 0xb890, 0x0010 }, + { 0xb890, 0x000a }, { 0xb890, 0x000e }, { 0xb890, 0x03f5 }, + { 0xb890, 0x0001 }, { 0xb890, 0x03ff }, { 0xb890, 0x0000 }, + { 0xb890, 0x0005 }, { 0xb890, 0x000a }, { 0xb890, 0x03f3 }, + { 0xb890, 0x0003 }, { 0xb890, 0x03f1 }, { 0xb890, 0x0003 }, + { 0xb890, 0x000c }, { 0xb890, 0x000e }, { 0xb890, 0x03fa }, + { 0xb890, 0x0007 }, { 0xb890, 0x0008 }, { 0xb890, 0x0010 }, + { 0xb890, 0x03ee }, { 0xb890, 0x000e }, { 0xb890, 0x03f6 }, + { 0xb890, 0x0007 }, { 0xb890, 0x03fc }, { 0xb890, 0x000b }, + { 0xb890, 0x03fb }, { 0xb890, 0x000f }, { 0xb890, 0x03f6 }, + { 0xb890, 0x0016 }, { 0xb890, 0x03f9 }, { 0xb890, 0x03ff }, + { 0xb890, 0x03ff }, { 0xb890, 0x0007 }, { 0xb890, 0x03fd }, + { 0xb890, 0x000d }, { 0xb890, 0x03fe }, { 0xb890, 0x0003 }, + { 0xb890, 0x03f1 }, { 0xb890, 0x000b }, { 0xb890, 0x0000 }, + { 0xb890, 0x0012 }, { 0xb890, 0x03fd }, { 0xb890, 0x03fc }, + { 0xb890, 0x0004 }, { 0xb890, 0x000f }, { 0xb890, 0x03ef }, + { 0xb890, 0x03f9 }, { 0xb890, 0x000d }, { 0xb890, 0x0002 }, + { 0xb890, 0x000c }, { 0xb890, 0x0003 }, { 0xb890, 0x0069 }, + { 0xb890, 0x0064 }, { 0xb890, 0x004f }, { 0xb890, 0x001e }, + { 0xb890, 0x03ed }, { 0xb890, 0x03dc }, { 0xb890, 0x03bc }, + { 0xb890, 0x03d1 }, { 0xb890, 0x03c5 }, { 0xb890, 0x03e4 }, + { 0xb890, 0x03ea }, { 0xb890, 0x03ff }, { 0xb890, 0x03fa }, + { 0xb890, 0x0007 }, { 0xb890, 0x03ff }, { 0xb890, 0x03e5 }, + { 0xb890, 0x03fa }, { 0xb890, 0x03f1 }, { 0xb890, 0x03f8 }, + { 0xb890, 0x03ef }, { 0xb890, 0x0007 }, { 0xb890, 0x0002 }, + { 0xb890, 0x0016 }, { 0xb890, 0x0001 }, { 0xb890, 0x000a }, + { 0xb890, 0x03f6 }, { 0xb890, 0x0000 }, { 0xb890, 0x03f7 }, + { 0xb890, 0x0004 }, { 0xb890, 0x0002 }, { 0xb890, 0x0010 }, + { 0xb890, 0x0004 }, { 0xb890, 0x03fd }, { 0xb890, 0x03f2 }, + { 0xb890, 0x03ee }, { 0xb890, 0x03fa }, { 0xb890, 0x03f1 }, + { 0xb890, 0x03fe }, { 0xb890, 0x03fb }, { 0xb890, 0x0008 }, + { 0xb890, 0x03ee }, { 0xb890, 0x000f }, { 0xb890, 0x03f0 }, + { 0xb890, 0x000f }, { 0xb890, 0x03f3 }, { 0xb890, 0x0004 }, + { 0xb890, 0x03f3 }, { 0xb890, 0x0003 }, { 0xb890, 0x03f5 }, + { 0xb890, 0x03fe }, { 0xb890, 0x03f5 }, { 0xb890, 0x0008 }, + { 0xb890, 0x03f7 }, { 0xb890, 0x000a }, { 0xb890, 0x03f9 }, + { 0xb890, 0x0000 }, { 0xb890, 0x03fb }, { 0xb890, 0x000c }, + { 0xb890, 0x03ec }, { 0xb890, 0x03fb }, { 0xb890, 0x03ee }, + { 0xb890, 0x000e }, { 0xb890, 0x03f5 }, { 0xb890, 0x0007 }, + { 0xb88e, 0xc128 }, { 0xb890, 0xf0f0 }, { 0xb890, 0xf0eb }, + { 0xb88e, 0xc166 }, { 0xb890, 0xeaea }, { 0xb890, 0xea0e }, + { 0xb820, 0x0000 } }; #define MAC_R25_MCU \