On Tue, Apr 23, 2024 at 08:58:16AM +1000, Jonathan Matthew wrote:
> On my NanoPi R5S, dwqe0 raises MAC counter interrupts after sending or
> receiving a few gigabytes of data.  The driver doesn't know how to clear them,
> so it causes an interrupt storm that makes the system almost unusable.
> 
> The simplest way to deal with this is to just mask off the counter interrupts,
> since we don't need them for anything.  The Linux driver does the same as
> far as I can tell.
> 
> I've tested this on the R5S, where it fixes the problem, and on a VisionFive 2,
> where it doesn't break anything.
> 
> ok?

The RK3568 TRM doesn't seem to have GMAC registers.

Intel documents them in:
Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series
Processors for IoT Applications
Datasheet, Volume 2 (Book 2 of 3)
Platform Controller Hub (PCH)
Document Number: 636722

10.2.190 MMC_RX_INTERRUPT_MASK -- Offset 70Ch
10.2.191 MMC_TX_INTERRUPT_MASK -- Offset 710h

In both, bits 31:28 are reserved.

We could write 0x0fffffff instead.  But the result is likely the same.

ok jsg@

> 
> 
> Index: dwqereg.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/ic/dwqereg.h,v
> retrieving revision 1.5
> diff -u -p -r1.5 dwqereg.h
> --- dwqereg.h	11 Nov 2023 16:32:56 -0000	1.5
> +++ dwqereg.h	22 Apr 2024 10:51:02 -0000
> @@ -83,6 +83,8 @@
>  #define GMAC_MAC_MDIO_DATA	0x0204
>  #define GMAC_MAC_ADDR0_HI	0x0300
>  #define GMAC_MAC_ADDR0_LO	0x0304
> +#define GMAC_MMC_RX_INT_MASK	0x070c
> +#define GMAC_MMC_TX_INT_MASK	0x0710
>  
>  #define GMAC_MTL_OPERATION_MODE	0x0c00
>  #define  GMAC_MTL_FRPE			(1 << 15)
> Index: dwqe.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/ic/dwqe.c,v
> retrieving revision 1.18
> diff -u -p -r1.18 dwqe.c
> --- dwqe.c	29 Mar 2024 08:19:40 -0000	1.18
> +++ dwqe.c	22 Apr 2024 10:51:02 -0000
> @@ -213,6 +213,8 @@ dwqe_attach(struct dwqe_softc *sc)
>  	/* Disable interrupts. */
>  	dwqe_write(sc, GMAC_INT_EN, 0);
>  	dwqe_write(sc, GMAC_CHAN_INTR_ENA(0), 0);
> +	dwqe_write(sc, GMAC_MMC_RX_INT_MASK, 0xffffffff); 
> +	dwqe_write(sc, GMAC_MMC_TX_INT_MASK, 0xffffffff); 
>  
>  	return 0;
>  }
> 
>