On Tue, Apr 23, 2024 at 12:57:33PM +1000, Jonathan Gray wrote:
> On Tue, Apr 23, 2024 at 08:58:16AM +1000, Jonathan Matthew wrote:
> > On my NanoPi R5S, dwqe0 raises MAC counter interrupts after sending or
> > receiving a few gigabytes of data.  The driver doesn't know how to clear them,
> > so it causes an interrupt storm that makes the system almost unusable.
> > 
> > The simplest way to deal with this is to just mask off the counter interrupts,
> > since we don't need them for anything.  The Linux driver does the same as
> > far as I can tell.
> > 
> > I've tested this on the R5S, where it fixes the problem, and on a VisionFive 2,
> > where it doesn't break anything.
> > 
> > ok?
> 
> The RK3568 TRM doesn't seem to have GMAC registers.
> 
> Intel documents them in:
> Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series
> Processors for IoT Applications
> Datasheet, Volume 2 (Book 2 of 3)
> Platform Controller Hub (PCH)
> Document Number: 636722
> 
> 10.2.190 MMC_RX_INTERRUPT_MASK -- Offset 70Ch
> 10.2.191 MMC_TX_INTERRUPT_MASK -- Offset 710h
> 
> In both, bits 31:28 are reserved.
> 
> We could write 0x0fffffff instead.  But the result is likely the same.
>
> ok jsg@

I suppose writing the additional bits will be useful as soon as the
bits stop being reserved on some future revision of the hardware.

ok by me as well.