Download raw body.
km_alloc(9), UAREA and kv_pageable
> Looks like amd64 is the only architecture that does that guardpage > thing. So I think this is fine. On that topic, it would be nice for at least all 64-bit arches with USPACE_ALIGN = 0, to always allocate UPAGES + 1 contiguous virtual pages for the u area, UPAGES physical pages, and make the lowest page's virtual address transation invalid. This has been on my todo list for a very long time, but ENOTENOUGHSPARETIME as usual. Maybe once I'm retired...
km_alloc(9), UAREA and kv_pageable