On Tue, Oct 6, 2026 at 1:29 AM Janne Johansson <icepic.dz@gmail.com> wrote:
>>
>>         radeondrm_setpal(rdev, ri);
>>         ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY;
>> +#ifdef __sparc64__
>> +       ri->ri_flg |= RI_BSWAP;
>> +#endif
>>         rasops_init(ri, 160, 160);
>>
>>         ri->ri_hw = rdev;
>> -#endif
>
>
> This feels like it should be guarded by an ifdef based on if the platform is big endian or not, and not just sparc64.

Hi Janne,

I checked this. Radeon already configures the framebuffer byte order
handling for big endian. The additional difference on sparc64 is that
it uses little endian pages for PCI framebuffer access. Mac and PowerPC
don't do that. SPARC has its own approach to handling PCI.

So I think this needs to stay sparc64, since the other platforms aren't
affected by this change, to my knowledge.

This is just from looking at the source tree. I only have SPARC and Intel
systems, so other people would have to test the PowerPC side. What I can
confirm is that this improves things on SPARC while maintaining the
current approach elsewhere. I think it's the smallest change that makes
a useful difference to start with.

-- 
Ted Bullock <tbullock@comlore.com>